Wednesday, 2019-09-25

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promachI mean how do I interface synth output from yosys to nextpnr-ice40 ?09:09
daveshah`synth_ice40 -json out.json`09:10
promachdaveshah : thanks. By the way, how to remove all ice40 DFF  in the case of using ltp command ?09:20
promachI mean for synth_ice4009:21
promachit is  ltp t:$_DFF_P_ %n   for  synth09:21
daveshahltp t:SB_DFF* %n09:21
promachdaveshah: what about for   synth_ice40    ?09:21
promachThanks, let me try09:22
promachERROR: failed to place cell '$abc$80826$auto$$84024_LC' of type 'ICESTORM_LC'09:26
promachPlacing design failed.09:26
promachdaveshah : I had this place error in nextpnr09:26
daveshahIs your design over utilised?09:27
promach   Number of wires:               651409:28
promach   Number of wire bits:          1495709:28
promach   Number of public wires:        116809:28
promach   Number of public wire bits:    909109:28
promach   Number of memories:               009:28
promach   Number of memory bits:            009:28
promach   Number of processes:              009:28
promach   Number of cells:               876909:28
promach     SB_CARRY                      40009:28
promach     SB_DFF                        23209:28
promach     SB_DFFE                       43209:28
promach     SB_DFFESR                    196809:28
promach     SB_DFFESS                      4009:28
promach     SB_DFFSR                      24809:28
promach     SB_LUT4                      544909:28
promachI am trying to fit into tinyFPGA BX09:28
promachthe previous error was for lattice 1k FPGA09:28
promachthe error below is for tinyFPGA BX09:29
promachERROR: failed to place cell 'data_input[21]$sb_io' of type 'SB_IO'09:29
promachPlacing design failed.09:29
daveshahSounds like you have too many IO pins09:29
promachdoes this mean pins overuse09:29
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ZirconiumXwq: Idea for bugpoint - a -grep-like argument for "interesting" crashes. For example, you might ask it to bugpoint an assert on a specific line, but dump anything which contains the phrase "ERROR: Assert"17:31
janrinzenumber of cells seems too much too..17:37
daveshahThat's cells from a Yosys point of view. Some carries LUTs and DFFs will pack together17:42
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janrinzedaveshah: the ecp5 board you were working on, is that available somewhere?18:08
daveshahNo, I'm afraid it isn't18:08
janrinzeit's like the versa but has hdmi and such, right?18:09
daveshahIt might be at some point in the future depending on how things work out18:09
tpbTitle: GitHub - daveshah1/TrellisBoard: Ultimate ECP5 development board (at
janrinzeyes, that one18:09
janrinzethe ulx3s has a different ecp5 chip18:09
janrinzeperhaps i should look into designing a daughterboard for the eval board from lattice18:10
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janrinzedaveshah: is there a tool to modify the BRAM in a ecp5 design like with ice40?19:34
daveshahNo, there isn't19:35
daveshahExactly the same concept could be used though19:35
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janrinzeECP5 support is relatively new, isn't it?19:35
janrinzeor has a lot smaller user base?19:36
daveshahAbout a year old19:36
daveshahCompared to 4 years for iCE4019:36
janrinzemakes sense19:36
janrinzei really like how nextpnr makes ecp5 like the big brother of ice40 now :-)19:37
emilyhm, how old is arachne-pnr? ~4 years too?19:39
daveshahYeah, icestorm came first and arachne-pnr shortly after19:40
sorearWhat did we use pre arachne?19:48
janrinzedaveshah: does nextpnr-ecp5 latch the output to I/O pins or do i have to do that explicitly?19:48
ZirconiumXwhitequark: Managed to trigger yet another assert in FlowMap: ERROR: Assert `!lut_gates[breaking_lut].empty()' failed in passes/techmap/
daveshahsorear: there was nothing, just tools to explore bitstreams19:49
daveshahjanrinze: no, it doesn't pack output registers automatically yet19:49
daveshahIf that's what you mean by latch?19:49
daveshahCurrently the output registers aren't supported at all19:50
janrinzedaveshah: Okay then I/O can have delay in respect to a global clock, right?19:51
daveshahFor now, a DDR primitive is the best bet19:52
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janrinzeI see. I am running a 1024x786 VGA output and it is decent. when using a dithered image it shows somewhat.19:53
janrinzeat almost 67 Hz refresh19:53
janrinzecould also be the pll of course.19:54
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janrinzedaveshah: DSP 18x18 mult is not inferred yet, right?19:55
daveshahNo, but it will be soon19:55
janrinze'automagically' ? :-)19:55
tpbTitle: DSP inference for Xilinx (improved for ice40, initial support for ecp5) by eddiehung · Pull Request #1359 · YosysHQ/yosys · GitHub (at
daveshahYup, for all multiplies above a certain size19:56
janrinzeI'll have a look at that.19:58
daveshahIt's a pretty monstrous PR because it includes Xilinx and iCE40 stuff too19:59
daveshahThe idea is about infrastructure for DSPs as much as anything else20:00
janrinzefor up5k I didn't mind to use the primitives. it was a little confusing at first to get it right but it works very well.20:02
daveshahYeah, when there are only 8 of them anyway instantiation isn't so bad20:03
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janrinzeOnly needed one for this design.20:04
janrinzeIt does have one DSP MULT18x18 now. so it looks like it works.20:06
ZirconiumXAfter entirely too many attempts, I now have a "minimal" repro for the FlowMap assert bug20:10
ZirconiumXWell, *a* FlowMap assert bug20:10
ZirconiumXGiven I turned up more in the process of finding this one20:10
* ZirconiumX updates Yosys, and it works fine20:20
* ZirconiumX sighs20:20
janrinzedaveshah: true dual port ram might be necessary to manually infer?20:29
daveshahYes, afraid so20:29
tntit's not called infer if you do it manually :)20:29
janrinzei noticed how yosys was struggling :-)20:29
ZirconiumXGood news: bug still exists20:41
ZirconiumXBad news: the test case I spent *hours* with bugpoint on doesn't trigger the bug in the current version20:41
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somlooh, xc7dsp now has a PR, neat!20:57
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