Tuesday, 2019-08-13

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FSM_DudeHey! Is this the right place to ask for help with Yosys? I'm using it for my studies, but I encounter some problem.11:33
FSM_DudeGreat! I already asked the question on SO, but did not have any luck with getting an answer there. I'm quite new to it, and I try to alter the FSM in the fsm_recode pass. If I do so, later on in the fsm_map pass yosys stops because an assertions is violated...11:36
ZirconiumXWhich assertion?11:37
tpbTitle: c++ - Yosys: How to correctly add states and transitions to fsm during fsm_recode pass? - Stack Overflow (at stackoverflow.com)11:38
FSM_DudeYes, that one.11:38
FSM_DudeI managed to get rid of the assertion in a nasty way, but that only made thing worse. Once I ran abc and dfflibmap it showed me that there were 0 gates and 0 wires...11:40
FSM_DudeWhat Im trying to do, is add redundant states to the fsm. Afterwards I want to see the area of the design. This way I can compare the overhead generated by the added redundancy11:41
ZirconiumXYou shouldn't need to hack into Yosys for it11:45
ZirconiumXAFAIK, it won't prune states that are used11:46
ZirconiumXSo if you have a one-hot state and then add a wildcard state at the end which does something, I think it'll handle that reasonably efficiently11:47
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FSM_DudeI don't follow, sorry11:55
pepijndevosThe symbiyosys docs mention only Z3 is mandatory, but say yices is the default prover... what's the deal there?12:02
FSM_DudeZirconiumX, this https://imgur.com/a/NiVJafL is basically what I try to achieve within the fsm_recode pass of Yosys12:05
tpbTitle: Imgur: The magic of the Internet (at imgur.com)12:05
FSM_DudeWould it be possible to add something like this to Yosys? Or is it impossible to alter the fsm within the c++ code?12:06
pepijndevosFSM_Dude, you're actually patching yosys to support a new type of FSM recoding?12:07
FSM_DudeI try to yes :)12:08
FSM_DudeI try to implement some fault tolerance into the FSM, and then analyse the overhead in terms of area etc12:09
FSM_DudeJust for my own research at uni12:10
FSM_DudeNow I'm wondering if it's even possible with Yosys lol12:10
pepijndevosThat's super cool12:10
daveshahI expect the problem is the size of `state_onehot` is wrong12:11
daveshahYou would need to look into where that is set, and perhaps resize it12:11
FSM_Dudedaveshah, indeed. I think I need to resize some stuff. Also the fsm_data.copy_from_cell() function has some boundaries on the state_in and state_out of the transitions...12:13
FSM_Dude            if (tr.state_in < 0 || tr.state_in >= state_num)                tr.state_in = -1;            if (tr.state_out < 0 || tr.state_out >= state_num)                tr.state_out = -1;12:13
FSM_DudeWoops, sorry for that format...12:13
daveshahYeah, I'm afraid I don't know the fsm stuff in Yosys well enough to help with the details12:14
FSM_DudeHmm okay! Thanks for the tip tho!12:14
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FSM_Dudedaveshah, that seemed to have fixed it :)12:45
FSM_DudeNow onto the next problem I face haha12:45
FSM_DudeThanks a lot!12:45
FSM_Dude27. Executing ABC pass (technology mapping using ABC).27.1. Extracting gate netlist of module `\test' to `<abc-temp-dir>/input.blif'..Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.Don't call ABC as there is nothing to map.Removing temp directory.12:47
FSM_DudeGuess I have a bigger problem than just the assertion lol12:47
daveshah`dump` and `show` are always helpful13:02
pepijndevosIn my experience, when you connect something wrong, Yosys is more than happy to optimize away the disconnected logic haha13:03
FSM_DudeThanks Im gonna have a look!13:08
FSM_Dudepepijndevos Hopefully my redundant states wont be optimized away... :P13:09
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cr1901_modernIt is a rite of passage to play a fun game of "guess why the FPGA synthesizer optimized away my whole design"13:28
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GenTooMancr1901_modern I am glad I got that out of my system several weeks ago I suppose.20:41
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daveshahIt shows how easy it is to determine a lack of side effects in hardware, tbh20:45
daveshahSoftware compilers tend to be much less keen/able to optimise large chunks of code away20:45
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