Wednesday, 2019-08-07

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pepijndevosCan Yosys (not nextpnr) give me my critical path?12:55
pepijndevosOr alternatively, how hard would it be to use the generic target for 74xx?12:55
tntyosys has no timing analysis or timing data12:56
pepijndevosNot even a simple unit delay something to synthesize for speed?12:59
tntnot that I know12:59
tntit's not timing driven synthesis at all.12:59
daveshahABC uses this stuff internally12:59
pepijndevosAh I see13:00
daveshahABC does do timing driven synthesis, using delay info from liberty files (for ASIC), unit delays (for `abc` LUT synthesis) or box/lut files (for `abc9` LUT synthesis)13:00
tntdaveshah: really ?  It optimize for depth ?13:00
daveshahHowever, `abc` doesn't count boxes (e.g. carries) in depth - but `abc9` does13:01
pepijndevos(what's the diff between abc9 and abc?)13:01
daveshahabc9 uses newer commands in abc that are capable of handling whiteboxes13:01
pepijndevosBut abc9 only does LUT, right?13:01
daveshahand uses a different format (xaig rather than blif) to better represent these whiteboxes13:01
daveshahYes, right now anyway13:01
pepijndevosSo can I extract this timing stuff from abc, or would it be easier to somehow use the generic nextpnr?13:03
daveshahYou probably won't get much of use from abc13:03
pepijndevosRight now 74xx liberty has no real timing info, but I want to get a rough idea of the maximum frequency of my 74xx CPU :)13:03
daveshahtbh topological timing analysis is sufficiently simple I'd just hack something together than trying to do it in nextpnr13:04
pepijndevosRight... just export to json and hack up some python13:04
daveshahjust toposort all your combinational cells and walk forward determining max delay13:04
tpbTitle: Topological sorting - Wikipedia (at
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daveshahIncidentally, the long term (end of the year at the earliest) plan is to represent timing information inside Yosys using `specify`blocks in the Verilog cell white/blackbox libraries13:06
ZipCPUdavehah: Really?  Wow.  I like it, but I am a bit surprised by the decision13:07
ZipCPUpepijndevos: If you are interested in critical path timing information from Yosys today, consider the LTP command.  It's not quite what you want, but it is related13:08
ZipCPULTP = Longest topological path13:08
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ZipCPUDon't forget to exclude FF's, since they aren't typically part of any actual timing chain13:09
pepijndevosWill -noff still work after techmapping?13:09
ZipCPUNot likely, but there are ways to still get it to work13:10
ZipCPU(If I remember them)13:10
ZipCPULet's see ... it was something like "ltp t:*FF* %n" IIRC, where you can replace *FF* with whatever you are using for FFs13:11
pepijndevosThat seems to work! But... the signal names are all like $abc$1375$auto$$47[15] so a bit hard to tell what it means13:17
ZipCPUYeah, exactly13:18
ZipCPUSo ...13:18
ZipCPUI talked with clifford about this, and got him to name both inputs and outputs of a FF with the name of the FF (usually found w/in the design)13:18
ZipCPUCheck for the first and last element in the LTP string, and that should help13:19
ZipCPUYou can also use "show" to figure out what's going on, perhaps even increasing the size of the incoming cone with something like "%ci1" or some such13:19
pepijndevosThe string I pasted was the last one... the first one is just a human-named signal13:20
pepijndevosShow is not a bad idea13:20
pepijndevosWhat's that bit about the incomming cone?13:20
ZipCPUThe incoming cone shows all the logic incoming to the currently seleected set of elements.  IIRC, %ci1 shows adds all the inputs to the current selection to the selection, %ci2 adds the inputs to those inputs and so on13:21
ZipCPUThere's also an outgoing cone that might be useful, %co with the numbers having the same meaning.  So you might consider adding %co1 to your LTP and see what happens13:22
pepijndevosoh, I can pass that to show you mean. Good idea... running show on the whole design.. takes a while.13:22
ZipCPUThat should help if the result was just before a FF and the name was still incomprehensible13:22
pepijndevosYay, %c02 actually shows the flip flop it goes to13:27
pepijndevosCan I somehow feed the output of ltp as the selection to show?13:28
ZipCPU... although I can't remember how to do it right now ... :/13:29
pepijndevosGoing over the help file it's not immediately obvious to me either. Maybe something with the select command?13:41
pepijndevosLooking at the source code I also don't see an obvious way to do it.13:44
pepijndevosExcept of course parse the output of the command and then convert it to a selection with a hacky Python script.13:45
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pepijndevosLol, ok, I made a *very* hacky script to do it
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tntpepijndevos: how many chips is that cpu ?15:02
pepijndevos82 last time I checked15:04
tntOh, that's reasonable.15:05
pepijndevosHrmmmmmm right now the longest part of the critical path is the logic from the alu output to the register depending on the state and the opcode.15:12
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pepijndevosomg, according to my rough estimate my cpu should be able to run at 10MHz. All 74AC chips seem to have a worst case delay of 10ns, so with a critical path of 9 and a worst case set-up time of 5ns...15:35
pepijndevosOf course in my bit serial archt that's only 0.5MHz instructions per second...15:36
pepijndevosTypical propagation delays are more like 5ns, so 20MHz is not impossible... maybe15:38
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pepijndevosHow well are source attributs preserved through synthesis? You could make a script that reports how many gates a line of code produced19:25
daveshahNot very well - ABC's architecture means that input code and gates produced don't correlate in any meaningful way19:33
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ZirconiumXCan somebody clarify the difference between $lcu and $alu? My understanding is that $alu is an adder/subtractor and a $lcu is a fast(ish) carry chain, but the line gets blurry when you need a carry chain for long additions20:46
daveshah`$alu` is usually the important one to map for FPGA things20:49
bwidawskis yosys smart enough to use carry chains in FPGAs for connected arithmetic units?20:51
daveshahWhat do you mean for "connected arithmetic units"?20:51
daveshahbtw, ZirconiumX, I just checked and nothing in Yosys should create a `$lcu` - but techmap will downmap a `$alu` to one20:52
bwidawskoutput of adders in ALMs (or whatever the generic term for that is)20:52
daveshahYes, stuff like + and - will become carry chains20:53
daveshahalthough this is more a function of the architecture techmap rules than Yosys itself20:53
bwidawskwell the attempt to use adjacent ALMs20:53
bwidawskI suppose that is part of PNR20:53
ZirconiumXShould be PnR20:54
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