Tuesday, 2019-08-06

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pepijndevoswhat are ANSI C style module declarations07:29
tntpepijndevos: I think were you declare the module ports not inside the () of the module, but later.07:32
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pepijndevosah I see.07:43
pepijndevosI never actually learned Verilog. To me it's just VHDL with C syntax and added WTF07:44
sorear…that’s the opposite of the distinction made in C07:44
daveshahYeah, ANSI in Verilog is the same as C07:46
daveshahEverything in the module header07:46
daveshahWith the "names in the module header, types below" style being non-ANSI07:46
tpbTitle: Port Declaration (at www.hdlworks.com)07:48
tntOh ok. Then I always use ANSI style then.08:02
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pepijndevosWelp... voodoo ahoy12:43
pepijndevosWhen I simulate my cpu in ghdl with a vhdl testbench it works perfectly12:43
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pepijndevosWhen I read it with verific/ghdl and convert to verilog and run it in ikarus, I get all sorts of borkennes12:44
pepijndevosInterestingly, different types of brokenness if I synthesize first or not.12:45
pepijndevosOdly synthesized seems less broken than not. The direct verilog output is just straigt away xxxxxxx12:45
tntDo you have an explicit reset ?12:46
pepijndevosYyyyyes? I don't reset all the signals though, only the ones I care about.12:47
tntAnd you're sure you haven't "forgotten" one ? :)12:48
tntAlthough sometime the 'x' propagation is a little agressive and doesn't detect that a result will always be deterministic no matter what the input is.12:48
pepijndevosEhhh, possible. I'll try if resetting all the things helps.12:49
pepijndevosBut why is this only an issue when converting to verilog?12:49
tntElse you need to actually look at the first 'x' that happens where it shouldn't and see why it's there.12:49
pepijndevosYea I guess12:50
tntpepijndevos: I have no idea how the conversion is done so I'm not sure if it's supposed to map to equivalent 'x' semantics or not ...12:50
pepijndevoshm ok12:50
pepijndevosAh it seems not so happy about metavalues. Understandable. I thought I'd let the compiler do its thing and output some don't cares.13:33
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pepijndevosdaveshah, I have an extremely weird issue, and could use some advice on ruling out a compiler bug if you have time. Basically my code breaks after doing techmap -map +/techmap.v; opt; but doing (n)one of the two is fine.14:34
daveshahpepijndevos: is this still involving x?14:34
daveshahanything else unusual?14:35
pepijndevosWell, it gives xxx after it optimizes away my design, but generally it's working without those two commands14:35
daveshahcan you post the ilang before techmap/opt?14:35
pepijndevosOther than that the target is 74xx logic, not really :)14:35
pepijndevosyea, will do14:36
pepijndevosdaveshah, https://paste.ubuntu.com/p/GS9KmpcGTx/14:39
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)14:39
daveshahOut of curiosity, what is getting optimised away14:41
pepijndevosHold on... some bits of the opcode... but at this point it's not actually broken yet... sorry, I was looking at the wrong thing to deretmine breakage14:44
pepijndevosSo it's breaking at a later stage, brb14:44
pepijndevosah, got it... more or less... it's something with muxes... will try to narrow it down14:46
pepijndevosBut in that case it's probably simply a bug in our mux techmap...14:47
pepijndevosI would like to do something like equiv_opt techmap -map ../74_mux.v, but first it gives me warnings about not having SAT models for all the things, and then it gives a lot of unproven $equiv. What's a good way to test this techmap is correct?14:51
daveshahSimulation before and after mapping?14:52
daveshahOr loading in models for all cells14:52
pepijndevosWhat do you mean?14:53
pepijndevosWell, pretty much I know it is *not* correct14:54
daveshahImmediately before equiv_opt, do `read_verilog` or `read_liberty` *without* -lib (unlike in normal synthesis) to load in models14:54
daveshahThen simulation of a simple design (just a mux on its own) is probably your best bet14:54
pepijndevosOh I see14:55
daveshahJust running synthesis of  a mux on its own might be enough to highlight the problem14:55
pepijndevosThanks, I'll give it a go :)14:56
pepijndevosEhhh, I get that I can use whitebox models for my techmap, but it'll probably still complain about $_MUX8_14:57
pepijndevosBut I'll figure it out I think...14:58
daveshahIf it's missing $_MUX8_ you could just give it this in a file: https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simcells.v#L324-L33215:00
tpbTitle: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com)15:00
pepijndevosoh, sweet15:01
daveshah oops I mean https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simcells.v#L287-L29415:01
tpbTitle: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com)15:01
daveshahof course15:01
pepijndevosone misplaced ' in the liberty file later...15:08
pepijndevosno, I'm still an idiot...15:09
pepijndevoscool Segmentation fault (core dumped) wat15:17
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pepijndevosI totally can't make it be happy about $_MUX4_ and still want to do the techmap16:16
pepijndevosI FOUND IT, I FOUND THE MISSING '16:43
pepijndevosand a way to check equivalence that kinda worked...16:48
pepijndevosZirconiumX, https://github.com/ZirconiumX/74xx-liberty/pull/17 phew, that was... something16:53
tpbTitle: Make sure muxes are correct by pepijndevos · Pull Request #17 · ZirconiumX/74xx-liberty · GitHub (at github.com)16:53
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ZirconiumXpepijndevos: so one of the inputs wasn't correct?16:55
pepijndevosZirconiumX, the MUX8 liberty model had a logic error. One of the dozen ' was in the wrong place16:58
pepijndevosAt least now it's *proven* that it's equivalent to the simcell.v one16:58
pepijndevosSo my CPU simulates correctly now in 74xx logic... that at least reduces the ways in which it can be wrong a bit.17:00
pepijndevosBut it would not catch ABC using a cell correctly that's defined incorrectly.17:00
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