Wednesday, 2019-07-24

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pepijndevosHow does the extract pass work with parameters?12:51
pepijndevos-ignore_parameters Do not use parameters when matching cells.12:53
pepijndevosSo what does it do to "use parameters"?12:53
pepijndevosIt seems extract is also extremely picky about using for example 1 or 8'b113:01
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pepijndevosDoes a techmap "inherit" the parameters of the thing it replaces?15:16
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pepijndevosAre there any magic rules for when a techmap matches or not? Mine does not, for some reason.15:57
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pepijndevosERROR: (ASSERT MODE) No matching template cell for type \$counter16 found.16:06
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ZirconiumX[16:07:31]  pepijndevos: Does a techmap "inherit" the parameters of the thing it replaces?16:15
ZirconiumXIf you use a _TECHMAP_REPLACE_ I think so16:16
ZirconiumX[16:48:29]  pepijndevos: Are there any magic rules for when a techmap matches or not? Mine does not, for some reason.16:16
ZirconiumXEither the module is named the same as the cell you're trying to replace, or you have (* techmap_replace = "target_cell" *) above it, and _TECHMAP_FAIL_ is zero16:17
ZirconiumXThat's when it matches16:17
pepijndevosZirconiumX, it's the dollar signs... If I'm trying to act cool and put dollar signs in my counter like a real techmap it fails16:22
pepijndevosIf I just extract and techmap without the dollars it breaks. I think I'm not escaping stuff enough/too much16:23
ZirconiumXThe documentation says techmap -assert errors out if a cell name doesn't end with an underscore16:24
ZirconiumXIf you called your cell $counter16, that'll error because it does not end with an underscore16:24
pepijndevos i think it means it'll ignore anything with an underscore if I read the code correctly16:25
tpbTitle: yosys/ at master · YosysHQ/yosys · GitHub (at
ZirconiumXConversely since your cell does not end in an underscore, it's an error16:25
pepijndevosYea, but if I just put an underscore it'll not error and still not replace, I think it's purely that it never asserts on underscored things.16:27
pepijndevosSo if I call my extracted cell counter16 and the techmap on counter16 all is good, but if I call my extraction $counter16 or \$counter16 or whatever, nothing works.16:28
pepijndevosOr even $_COUNTER16_ or anything else that I've tried.16:29
pepijndevosSo I'm not understanding anything about the naming convention and escaping. Like, I've seen \$thing and \\$thing and $thing in various places16:29
pepijndevosI guess I don't really care about the dollar thing, except counter8 seems so common it might come up in normal code, so I thought I'd stick with what seems to be a convention for dollar signs for cells.16:30
pepijndevosShould I just call it 74xx_counter and be done with it?16:31
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pepijndevosCool, techmap kinda works, simulation super broken.16:52
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pepijndevosit's working! Kinda??17:28
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ZirconiumXpepijndevos: so when are you shipping a PicoSoC to me?17:32
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pepijndevosZirconiumX, hopefully near the end of the holiday :^)17:50
ZirconiumXI think the multiplier would be painful17:50
pepijndevosThe pwmled is now 7 chips17:50
ZirconiumXBecause of counter recognition?17:50
pepijndevosBut it's extremely picky, so you pretty much have to want to use it.17:51
pepijndevosOriginally I wanted to use an up/down counter, but it seems 74161 is pretty much the only thing that's still on sale.17:51
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ZirconiumXI don't think you can meaningfully reduce that benchmark any further17:52
pepijndevosWith an up/down counter you could make a sweeeet stack pointer, but at least maybe this is somewhat useful as an instruction pointer.17:52
pepijndevosThere is a sexy sexy 8-bit up/down counter IC, but I don't think it's sold anywhere.17:53
ZirconiumXWhich model?17:53
ZirconiumXpepijndevos: have you seen the 74x4040?17:59
pepijndevoseh, yea... can't remember the details18:00
pepijndevos12 bits is a bit... odd, no preset, no up/down. So it could be a lot more efficient in some cases, and less useful in others.18:02
pepijndevosRight now I have to specifically extract counter8, counter16 etc. and counter12 seems... not very common.18:03
pepijndevosSo for example, if I want to use it as an instruction counter, I need preset for jumps18:05
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pepijndevosAlthough I'm not even convinced what I'm doing now will work for that...18:06
pepijndevosWell, lemme push and you can have a look at it.18:06
GenTooManthe 74hc191 still is produced?18:08
ZirconiumXTrue, and Farnell sell it18:11
ZirconiumXGenTooMan: though we prefer DIP over SOIC for this18:11
GenTooManZirconiumX Nexperia and TI still make the DIP version as far as I know.18:12
sorearkinda surprised you’re not just using quad nands etc18:12
ZirconiumXTI are the one who sell DIPs for Farnell, and it's on back-order18:12
ZirconiumXsorear: We're crazy not stupid18:12
GenTooManat least you are not making it with transistors.18:15
pepijndevos74x191 is actually a nice one maybe? Not really in AC or DIP but... it counts down.18:19
GenTooManthe reason I bothered pointing it out.18:19
*** Thorn has joined #yosys18:24 petition: TI makes the whole 74xx series18:30
pepijndevossorear, part of me wants to do NOR and recreate the Apollo Guidance Computer18:31
daveshahWhy need a petition when you have MPWs?18:31
pepijndevosdaveshah, what's MPW?18:32
daveshahMulti project wafer18:32
daveshahRelatively cheap way of making custom silicon18:32
pepijndevosAre you suggesting I make an ASIC instead (boring), or produce my own 74xx chips (omg)?18:33
pepijndevosAny idea what it costs to do that kind of stuff?18:33
daveshahProbably a few thousand euros minimum18:34
pepijndevosOkay, scrap the, on to kickstarter hehe18:34
GenTooManthen your biggest issue would become buffering and someone to package the chips. a single 8 inch wafer can get you quite a few parts I suspect.18:35
daveshahEuropractice 700nm, probably fine for any 7400, 300€/mm2, 5mm2 min18:36
daveshahFor 30 samples, excluding packaging18:36
ZirconiumXThat's a bit pricey, but would be funny18:37
ZirconiumXOn the other hand, why not just fabricate a PicoSoC directly?18:37
pepijndevosThat's what these Raven people did, no?18:38
pepijndevosOr why not both?18:38
daveshahThat's already been done18:38
ZirconiumXpepijndevos: I'm going to disappoint you greatly18:39
ZirconiumX"In my experience writing counter + 1 and counter + 1'b1 already causes a mismatch"18:39
ZirconiumXBecause 1'b1 is 1-bit, and 1 is 32-bit18:39
pepijndevosI know, but yosys optimizes the useless bits away18:40
ZirconiumXSure, but they're semantically different and the compiler obviously has to keep semantics18:40
pepijndevosI guess...18:41
daveshahopt and wreduce should deal with the difference though18:41
pepijndevosIt just makes the counter extraction not very flexible.18:41
ZirconiumXI'm reasonably sure Yosys turns, say, 4'b1 (i.e. 4'b0001) to 4'bxxx118:41
ZirconiumXBut don't quote me on that18:42
pepijndevosdaveshah, if I put my extract pass *after* wreduce it doesn't match.18:42
daveshahWhat does the netlist look like after wreduce (`dump` and `show` are helpful)?18:43
daveshahYou might want to use a wreduce'd counter (e.g. saved as il) as the needle in this case18:43
pepijndevosThat might be a good one...18:44
daveshahAfter wreduce and clean, this produces three identical adders (A_WIDTH 4, B_WIDTH 1, Y_WIDTH 4, B connected to 1'b1)18:46
tpbTitle: Snippet | IRCCloud (at
pepijndevosdoes opt do clean or are these different things?18:49
daveshahopt does clean too (I didn't use opt for this test as it would actually merge all three adders)18:50
pepijndevosyay that works18:53
pepijndevosNow I wonder if it gets used in *any* of the other benchmarks...18:53
pepijndevosThe answer is no18:54
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matt`hello! i'm having some trouble understanding a yosys error message: "found error in internal cell" where it's complaining about cell $_DFF_PP1. I'm experiencing this when running `synth_xilinx`; `read_verilog` works fine (although I do get a warning about tri-state logic from the same file triggering the error message). Is there a possibility this error means I'm using a tristate representation not supported by yosys? What does that21:42
matt`error mean generally? That yosys isn't able to map the RTL to the available Xilinx cells?21:42
matt`i'm running the current git master version btw21:43
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daveshahmatt`: I don't think this would be related to a  tristate issue21:47
daveshahA "found error in internal cell" is a Yosys bug21:47
daveshahIf your design isn't confidential, creating a Yosys issue would be helpful21:48
matt`daveshah: i'll try to get this down to a minimal example and raise the issue. Thanks for the help! By the way, what does it mean that tri-state has limited support? is there somewhere in the documentation that says what is and isn't supported in that regard?21:49
daveshahIf it helps pinpoint the issue, a `$_DFF_PP1_` is the Yosys internal type for a single-bit D flipflop with an asynchronous set and rising edge clock21:50
daveshahIn practice I don't think it's so much that only a subset of tristate functionality is supported, as that tristate has a lot of different possibilities and not everything has been tested21:51
daveshahThis is particularly the case for the Xilinx flow which isn't so well used for designs with this kind of stuff21:52
matt`gotcha. thanks again21:54
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