Saturday, 2019-07-20

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pepijndevos_Warning: Yosys has only limited support for tri-state logic at the moment. (../benchmarks/MCPU.v:61)10:20
pepijndevos_Trying to synthesize and failing10:20
tpbTitle: MCPU/MCPU_0.1a.v at master · cpldcpu/MCPU · GitHub (at
tntpepijndevos_: yeah. "assign data   = states!=3'b001 ?  8'bZZZZZZZZ : accumulator[7:0]; " needs some change.10:26
tntAlso, is that supposed to be a top level ?  I mean tristate really only makes sense for IOs. No modern fpga has internal tristates.10:27
corecodeyea too bad that there is no easy way to communicate an output enable other than explicit second line10:27
corecodebut i guess it makes it more explicit10:27
pepijndevos_tnt, not totaly sure tbh, just some core I snatched from the web.10:29
corecodetnt: do you think it would make sense to automatically convert tristates to (hidden) enable signals and then connect to buffer OE?10:32
corecodeseems messy and too implicit10:32
corecodevery behavioral, not RTL10:32
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maikmertenwith latest yosys master LUT usage is back to normal (nextpnr can pack things together nicely again)12:16
maikmertenso thanks a lot! :-)12:16
maikmertenwith relut being at work and nextpnr being able to pack things again, LUT-usage overall is now lower than ever12:24
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maikmertenf_max is also back to normal, which means ~35 MHz (which I'm used to, caused by a carry chain) vs. ~45 MHz (with the original relut branch merged, with the carry chain no longer being the critial path). I wonder how the pre-fix yosys/nextpnr flow managed that.12:33
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pepijndevos_Huh, I'm confused. Looking at rtlil.h I swear I saw the actual implementations of add* functions, but I can't find them. I guess I'm being thick.15:03
pepijndevos_git grep addAdd does not seem to find any actual implementation.15:03
pepijndevos_oh, addAdff is there alright... but where are the others...15:05
pepijndevos_ah... DEF_METHOD15:06
pepijndevos_Is $mux always two-way? Because there is a $_MUX4_ but I've never seen $mux4, yet in rtlil.h it seems only two-way.15:11
daveshahLarger muxes would end up either as $pmux or $shiftx depending on coding style15:12
daveshahOr perhaps even a tree of $mux if coded using a tree of ?:15:13
pepijndevos_ah ok15:14
pepijndevos_I was looking at this code
tpbTitle: ghdlsynth-beta/ at db6d9f374de1eb1c074c2b9828bc6d99055b3624 · tgingold/ghdlsynth-beta · GitHub (at
pepijndevos_For a mux4 it indeed creates a tree of muxes, and was curious if that's the correct way to do it.15:14
daveshahIt's as good as any15:15
daveshahI'm not sure why ghdl has a mux4 cell in the first place...15:15
pepijndevos_I'm going to try to add module instatiations. We'll see if just adding it as a cell and connecting wires does the job.15:16
daveshahYes, modulo parameterisation15:16
pepijndevos_I think that's handled on the ghdl side, but not totally sure. Tristan mentioned he implemented modules in synthization but not on the yosys side, so I thought I'd try doing something useful.15:18
daveshahFor anything that isn't a blackbox leaf cell, you'll probably want to strip parameters from the instance and give each parameterised variant a unique name15:19
maikmertenis there a list of nextpnr python console commands?15:28
daveshahNo, unfortunately not15:31
maikmertenah, okay :-)15:33
daveshahFor querying the Arch database you can follow
tpbTitle: nextpnr/ at master · YosysHQ/nextpnr · GitHub (at
maikmertenjust wondering if there is a way to highlight critical paths in the graphical overview15:34
maikmertenbut perhaps stuff like that is not what the python console is actually meant for15:34
maikmerten(I imagine it's more for orchestrating processing steps)15:34
daveshahNo, unfortunately there's no Python or C++ api to get critical paths yet15:35
daveshahThe timing stuff isn't really integrated very well15:35
maikmertenit's still plenty neat :-)15:36
maikmertenhelp() at the time being is a halt-and-catch-fire alias15:38
maikmertenI guess that's because it's doing interactive stuff with stdin and stdout presumably15:39
daveshahTab completion should work15:40
maikmertenit does!15:40
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pepijndevos_What's a blackbox module supposed to look like in `dump`? Currently ghdl just makes a module \name end16:40
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daveshahIt also needs ports and a blackbox attribute set on it16:40
pepijndevos_I thought as much... some work to do then.16:42
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