Tuesday, 2019-07-16

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pepijndevos_Could anyone knowleable weigh in on how to implement module instantiation in a VHDL frontend? https://gitter.im/ghdl1/Lobby06:55
tpbTitle: ghdl1/Lobby - Gitter (at gitter.im)06:55
pepijndevos_I think the current approach is to just synthesize the whole hierarchy in ghdl, but I don't think this allows using hardware primitives or mixing vhdl and verilog.06:56
pepijndevos_If I load a verilog file that references another, it just puts that in as a cell. Is there any extra work required on the ghdl side to do that, or as soon as a module is in ilang all is good and hierarchy will be handled by yosys?06:58
pepijndevos_How is this handled around implementations? In vhdl an entity can have multiple implementations that you can select.07:00
daveshahI don't know about implementations07:03
daveshahBut the problem is parameterisable modules07:03
daveshahAt the moment read_verilog stores the Verilog AST as well as creating RTLIL07:03
daveshahIf the hierarchy command encounters an instance of a module with non-default parameters (and a set of parameters not seen before), then it will rerun elaboration with those parameters07:04
daveshahIf you only want to handle VHDL instantiating Verilog modules or blackbox cells (eg FPGA cell instantiation)07:05
daveshahThen elaborating the whole hierarchy in ghdl and leaving unknown modules as blackbox cell instantiations would work07:05
daveshahThis wouldn't handle the case of a Verilog module instantiating a VHDL module though07:06
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pepijndevos_daveshah, ah thanks. Is that how verific does it as well?10:16
pepijndevos_ZirconiumX, I can now generate my PWM pcb from VHDL, except it adds a ton of buffer chips. So that's good progress, but it'd be nice if we could tell ABC to not do that.10:27
pepijndevos_It's weird that it adds more of them than the same code in verilog10:27
pepijndevos_Looking at "show" they are all on the reset lines in this case, but not on the clock. Hmmm indeed10:32
pepijndevos_The hacky solution is of course to do what you suggested and just short them when generating the kicad netlist. Or maybe we could make a techmap that is just a wire.10:36
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pepijndevos_ZirconiumX, holy shit, I updated yosys and all 74xx benchmareks are *much* less chips now. Hmmmm https://twitter.com/whitequark/status/115082941932336332813:16
ZirconiumXMaybe it's proc_prune?13:18
pepijndevos_Dunno but I'm not complaining :)))13:19
pepijndevos_Some of them are tempting to be built now. Still quite rediculous, but 370 chips for a 6502...13:23
ZirconiumXThat's reaching the realm of feasibility13:24
ZirconiumXBut it's not as good as a human there13:24
pepijndevos_How much chips does it take a human to build a 6502?13:25
tnt1 ?13:28
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