Saturday, 2019-07-13

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sorearright, it’s not emulating a latch, it literally is one00:09
sorearit is synthesizing a latch from smaller components that are not themselves latches00:10
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cr1901_modernWhat does a latch from smaller components look like then (note that yosys has a $dlatch cell, so it wouldn't go the "back to back NAND gates" route)?00:13
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sorearI’d say a LUT programmed as a 2:1 mux, with the output fed back as one input00:31
cr1901_modernThat seems reasonable to me too. I'm doing a few experiments where I modify an ilang input (that was created from a "real" Verilog latch) and see what cells yosys infers00:34
cr1901_modernOne of them was a mux w/ feedback00:35
cr1901_modernI think00:35
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maikmertenhmmm... did something significant change within the last two weeks regarding yosys and nextpnr for the iCE40? My SoC went from ~2500 to ~3000 LCs, but f_max increased from ~35 MHz to ~40 MHz17:32
maikmertenso that's quite something17:33
tnt-relut was enabled by default yesterday.17:37
tntbut ... I wouldn't expect that from it.17:38
maikmertenah, interesting17:39
maikmertenis there a description on what it does?17:41
maikmertenI'm invoking synthesis with "yosys -p 'synth_ice40; attrmvcp; write_json ./boards/hx8k-breakout/top.json'"17:42
maikmertenis there a simple way to disable relut for testing?17:42
tntnot really. I think the easiest is just to look at all the passes of synth_ice40 and call them manually and skip the unlut.17:43
maikmertenewww. ;-)17:44
maikmertenI mean, the f_max is great, but I figure a noticable LC-increase was not anticipated?17:44
tpbTitle: synth_ice40: switch -relut to be always on by whitequark · Pull Request #1183 · YosysHQ/yosys · GitHub (at
tntmaikmerten: well, relut should yield a LUT decrease really ...17:45
maikmertenyeah, it does say merging and stuff17:45
maikmertencompiling (pre-enabling) to see if that makes a difference17:49
tpbTitle: synth_ice40: fix help text typo. NFC. · YosysHQ/[email protected] · GitHub (at
maikmertenyup, going back to that commit brings LC-count back to ~250018:00
maikmertenand f_max back to ~35 MHz18:01
tntmaikmerten: and if you do synth_ice40 -relut with that version you see the LC increase ?18:11
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tpbTitle: debian Pastezone (at
maikmertenso relut *does* reduce the LC count18:21
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maikmertenbut nextpnr doesn't pack things as tightly anymore18:21
daveshahOh I think I know the problem18:22
daveshahThe LUT map ordering changed to accommodate abc918:22
daveshahThis will cause the relut changes to no longer allow the LUT and carry to be packed together18:22
maikmertenoh :-)18:23
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tntdaveshah: what do you mean by lut map ordering ?18:24
daveshahThe $lut to SB_LUT port mapping18:25
tpbTitle: yosys/cells_map.v at master · YosysHQ/yosys · GitHub (at
daveshahabc9 maps such that LUT input 0 should be the fastest18:25
daveshahBut SB_LUT input 3 is the fastest18:25
daveshahafk right now, so can't look in detail18:25
maikmerten(is it useful if I provide my test case?)18:25
maikmerten(as in the .json files with and without relut, the Verilog stuff is MIT licenced anyway)18:26
tntmaikmerten: can you open an issue so this can get tracked ?18:27
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maikmertenis this a nextpnr or yosys thing?18:27
tntAh well, this might be  already18:27
tpbTitle: -relut appears to cause performance problems with ice40 synthesis · Issue #1187 · YosysHQ/yosys · GitHub (at
maikmertenI suspect former18:27
tntit's a yosys thing.18:28
maikmertenokay, I see a similar LC ballooning thing there18:28
maikmertenin my case, I at least get a wonderful f_max increase18:29
tntMost likely your critical path was not an adder. But in picorv32 I know the critical path has a carry chain in it.18:30
maikmertenas far as I can tell my critical path is a subtraction, so there's a carry in there somewhere ;-)18:33
tpbTitle: debian Pastezone (at
tntmmm, ok yeah, not all adders will be 'changed' by relut I guess.18:35
maikmerten(yeah, 33 bit subtraction for "less than unsigned" cpu_inst.alu_inst.ltu)18:35
maikmertenbut the dramatic increase in f_max (veeeeeery nice) makes me wonder what it looked like before18:37
tpbTitle: diff --git a/techlibs/ice40/ b/techlibs/ice40/ index - (at
tntmaikmerten: can you give that a shot ?18:38
maikmertentnt, on yosys master?18:40
tntmaikmerten: you can apply it on what you're using now and just check with -relut option.18:44
maikmertentnt, sorry for my stupidity, but is this something "git am" should apply or is this a "raw" diff?18:48
tntthat's a raw diff18:49
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maikmertenpatching file techlibs/ice40/ice40_unlut.cc18:54
maikmertenpatching file techlibs/ice40/synth_ice40.cc18:54
maikmertenpatch unexpectedly ends in middle of line18:54
maikmertenHunk #1 FAILED at 344.18:54
maikmerten1 out of 1 hunk FAILED -- saving rejects to file techlibs/ice40/
maikmertenwill manually replicate18:58
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tpbTitle: debian Pastezone (at
maikmertenthat brings down LC usage compared to no relut19:06
maikmertentoo bad f_max is back to normal ;-)19:07
maikmertenbut one cannot have everything19:07
maikmerten(the subtraction carry chain is the critical path again)19:08
tntmaikmerten: did you try --placer heap ?19:08
maikmertentnt, yup, it's my default placer19:09
maikmerten        nextpnr-ice40 --randomize-seed --placer heap --hx8k --json top.json --pcf hx8k-breakout.pcf --asc top.asc --freq 2819:09
tntOTOH the fmax doesn't mean much because you ask for 12 MHz ... so it will stop even searching for anything better.19:09
maikmertenoh, in the past I didn't really an effect on f_max when asking for a higher frequency19:10
maikmertenbut then again, I didn't try that in a while19:10
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maikmertenyeah, asking for 40 MHz (which appears to be attainable with yosys master by accident) doesn't really move things19:13
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tntwhat soc is it btw ?19:23
tpbTitle: GitHub - maikmerten/spu32: Small Processing Unit 32: A compact RV32I CPU written in Verilog (at
maikmertentnt, it can do
tpbTitle: badapple.mp4 - Google Drive (at
maikmertentnt, I'm using the HX8K breakout board, with some custom additions:
tpbTitle: IMG_20190623_211623362.jpg - Google Drive (at
maikmerten(I need to update that block diagram, the VGA unit is not text mode anymore)19:28
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