Wednesday, 2019-07-10

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f003brvjust curious, has anyone ran into issues running iceprog on newer Macs?04:32
sorearif someone had, you'd probably get a reply somewhere before asking for the fifth time04:34
f003brvkk this is why no one likes you04:37
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pepijndevos_ZirconiumX, I tried adding the 74HC30 and it does not get used at all... even if I write out ~&counter11:05
pepijndevos_But maybe I effed up the liberty logic. I just copied the 4-bit logic and extended it. I'm honestly not 100% sure if a multi-port NAND is all ANDS with a not in the end, or a tree of NANDs.11:09
daveshahABC often struggles to map gates with a large number of inputs, I think because of how it extracts gates in the netlist it becomes harder and harder to find a match11:21
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daveshahAIUI it would be a tree of ANDs with a not at the end11:21
pepijndevos_In that case 4-bit NAND logic seems wrong?
tpbTitle: 74xx-liberty/74series.lib at master · ZirconiumX/74xx-liberty · GitHub (at
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pepijndevos_(same for 3)11:30
ZirconiumXIt might be,11:30
pepijndevos_The datasheet suggest something more exotic with NOR gates and inverters. huh
pepijndevos_Ah, I guess it's that one identity where A+B=(A*B)' or something like that11:34
pepijndevos_Yea, so if I'm not mistaken the inverters and nor is the same as an and gate, so daveshah is correct. Will make PR.11:37
pepijndevos_Yosys did *not* like my attempt to explain it a JK flip-flop btw haha11:37
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pepijndevos_What's the deal with pmux2shiftx and shregmap? Which one do I want for mapping to a 74xx shift register?13:50
daveshahIf it is a fixed length shift register, you will want shregmap followed by a custom techmap rule13:55
daveshahFor variable length shift registers, running pmux2shiftx first will allow a few more coding styles to be mapped but is not essential13:55
pepijndevos_What is a pmux even hehe13:55
daveshahparallel mux13:56
pepijndevos_But I think I want shregmap indeed13:56
daveshahpmux has one-hot (ish, anyway) select inputs13:56
pepijndevos_"The generated shift register will be of type $__SHREG_DFF_[NP]_ and will use the same interface as the original $_DFF_*_ cells."13:57
pepijndevos_Ehhhh, how does one SHREG have the same interface as a chain of DFF? In particular not 100% sure how it works with serial/parallel input. A chain of flip-flops would support parallel output, and maybe parallel input, right?14:00
ZirconiumXpepijndevos_: Because a SHREG (shift register) *is* a chain of DFFs14:01
pepijndevos_sure sure, just in terms of verilog interface.14:02
pepijndevos_ from this is looks like you can really only set the input and get the output.
tpbTitle: yosys/shregmap.v at 6d74cf0d2b903eae16372f58dc15e4bc67666a2b · YosysHQ/yosys · GitHub (at
daveshahMost FPGA shift registers have one input and one or two outputs (some have a fixed and variable length output)14:05
daveshahYou might be able to use the "tech" feature of shreg to add some custom mapping rules for sipo at least14:05
tntAnyone knows what trying to call a task in a 'for' loop seems to not work at all ? Are you not supposed to do that ?  (this is test-bench code)14:09
pepijndevos_Hmmm, as far as I can tell you can only set it to xilinx or greenpack, or you mean patch yosys to support a tech 74xx option? XD14:09
daveshahYes, patch yosys14:10
pepijndevos_For counter extraction that goes both ways, yes, but for a very specific feature for a target that so far only 2 people care about, hmmm, let's just stick to fifo for now.14:13
pepijndevos_I'll probably bug you about the counter pass later hehe14:14
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pepijndevos_Seems the 74AC164 is the most common/available type14:41
pepijndevos_How does the enable thing work in shregmap?15:14
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pepijndevos_And uuuh, does it matter where in the process I run shregmap and the techpass? Seems I broke everything...15:18
pepijndevos_Basically now I have mostly lower-case things at the end.15:19
pepijndevos_Uhm, ok, fixed that, but not a single shift register is initiated.15:24
daveshahSo you will want a general techmap first, then shregmap, then a techmap for shift registers15:29
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pepijndevos_    assign led = counter[0];15:44
pepijndevos_    always @ (posedge clk)15:44
pepijndevos_        counter <= {1'b1, counter[7:1]};15:44
pepijndevos_Is that a reasonable shift register?15:44
pepijndevos_Doing this after that tells me it converted no shift registers:15:45
daveshahI think so15:45
pepijndevos_techmap -map +/techmap.v15:45
pepijndevos_shregmap -maxlen 8 -clkpol pos15:45
pepijndevos_techmap -map ../74_shreg.v15:45
pepijndevos_Converted 0 dff cells into 0 shift registers.15:46
daveshahWhat is the full code?15:47
daveshahYou might also need a opt_clean after the first techmap15:47
pepijndevos_Hm, will try and then make a paste, or just commit all the broken stuff to a branch.15:48
pepijndevos_no change15:48
pepijndevos_I had initialised the counter...15:50
pepijndevos_Ok, so it works, but has very limited applications. Basically you can't do a parallel read/write or initialise/reset it.15:52
pepijndevos_The chip has a global reset and enable, is there any way to expose that?15:52
daveshahThe enable can be used with -enpol to shregmap15:53
daveshahResets aren't supported as no FPGA shift register I know supports reset15:54
pepijndevos_What if you do -match $_DFFSR? hehe15:57
daveshahIt might work, but I wouldn't rely on it15:58
daveshahIt's possible some nasty combinations like self resetting shift registers could missynthesise15:59
pepijndevos_eh, I'm not even sure what code to write to make it want an enable.16:03
pepijndevos_I thought I'd wrap the shift in an if, but that just make DFF with MUX16:05
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daveshahYou probably need a dff2dffe to turn DFF with MUX into DFFE17:50
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pepijndevos_daveshah, there are two of them already, even more? haha
tpbTitle: 74xx-liberty/synth_74.ys at master · ZirconiumX/74xx-liberty · GitHub (at
pepijndevos_eh, my version lives here:
tpbTitle: Shift register pass by pepijndevos · Pull Request #12 · ZirconiumX/74xx-liberty · GitHub (at
pepijndevos_Oh wait, the second one undoes the dffe, why is that ZirconiumX?18:39
pepijndevos_Ah I guess because our DFF are much more area efficient18:40
pepijndevos_Eh.. 74377 seems fine to me. I mean it's half the pins of the 7416374, but it's also half the pins ;) (so chip count is worse, but area is about the same, except now with extra muxes)18:43
daveshahIn any case you want to be running dff2dffe, particularly with unmap-min-ce, after doing a generic techmap run18:43
pepijndevos_Why *with* unmap-mince? Doesn't that go back from dff to dff+mux?18:44
daveshahYes, if ce is used less than a certain number of times18:46
daveshahBecause each chip shares ce between 8 DFFs18:46
daveshahYou probably want to do the unmap after mapping shift registers18:46
pepijndevos_ah I see, so what it does is that if there are 5 DFFE with one clock enable, it'll not make a whole chip for that.18:48
pepijndevos_Well, removing the mince made the shift register enable work. Althoug weirdly enouhg, it makes a NOT gate and a PP rather than a negative enable. Well, fine with me. Only thing I need to figure out is the correct order of things.19:07
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pepijndevos_Eh... ZirconiumX as far as I can tell, the unmap-mince makes everything just worse. Saves about 700 chips total by removing it.19:19
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pepijndevos_huh... why is there a lowercase $dff in my output...19:38
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