Tuesday, 2019-07-09

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develonepi3Hello All On a Raspbian GNU/Linux 9 (stretch) I have a working nextpnr-ice40 ver 7d5dba3. I upgraded to Raspbian GNU/Linux 10 (buster). The versions of gcc version 6.3.0 (stretch) gcc version 8.3.0 (buster). My ver of nextpnr-ice40 compiles and runs on my RPi3B+ (buster). It does not create the catzip.asc & catzip.bin files. My nextpnr-ice40 fails at iteration 200.  My arachne-pnr (buster) does create catzip.asc & catzip.bin files. Thanks in12:13
develonepi3advance. Any help is appreciated.12:13
ZirconiumXWhat do you want help *with?*12:18
ZirconiumXThat nextpnr does not converge?12:19
develonepi3Yes it gets to 4 nets and 43 arcs and fails.  I am running with -f at present time.  4 nets 8 arcs.12:28
daveshahWhat design is it? How utilised is the FPGA? Have you seen if a different seed will work?12:30
tntjust how full is that design ?12:30
develonepi3It is HX8K running a zipcpu on cat-board with sdram 72%. I have not tried a different seed. What should I use for arg --seed arg?12:35
ZipCPUIf it's working, then leave the seed argument off12:35
daveshahIt's not working12:37
daveshahJust try values from 2 upwards for --seed12:37
ZipCPUAre you using nextpnr?12:38
* ZipCPU reads history12:38
develonepi3Yes nextpnr-ice40 failed at iteration 200 did not meet 4OMHz with -f option.12:42
tntdevelonepi3: did you try HeAP ?12:43
tnt--placer heap12:43
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develonepi3I tried to upgrade nextpnr adding eigen3-dev it would not compile I --placer heap must be a new option.12:46
ZipCPUDid you try building nextpnr with "make -j1" (after the cmake command)12:47
ZipCPU... that is, to build the updated nextpnr?12:48
develonepi3Yes it would fail about 10%12:48
develonepi3Anything greater than 1 locks the RPi.12:49
ZipCPUHow much RAM does your RPi have?12:49
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ZirconiumXIt's a 3B+, so 1GB12:51
develonepi3My Pi is just a 1G waiting to get my Pi4 with 4G12:51
ZipCPUThat'd be tight.  How about creating a large swap device?  So whatever doesn't fit in memory gets swapped to disk?12:52
ZipCPUThere are network options for off board storage if necessary.  It might end up being slower than molasses, but is should still work12:52
develonepi3I already did that 100 to 1000 swap since that was need to build bare metal (FPC & Lazarus) software for the Pi12:53
ZirconiumXZipCPU: faster than pitch, though!12:54
develonepi3I don't think it is a memory issue since on 73.9 swap is used 648.1 free. from12:59
tntNo one packacked nextpnr yet ? (with builds on ARM)13:01
develonepi3The ver nextpnr-ice40 on buster 205442812 is bigger stetch 195635244 I guess since all the boost packages were bumped up 1.62 to 1.67.13:06
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develonepi3Hello all made a mistake MiB Swap: 1000.0 total, 927.6 free, 72.4 used. 644.2 avail Mem14:42
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develonepi3Hello All: I was able to get a catzip.bin on (buster) raspbian RPi3B+ with nextpnr-ice40 --seed 8 --freq 40 --hx8k --pcf $(PCFFILE) --json catzip.json --asc catzip.asc in the Makefile [email protected]:~/testbuilds/tb/catzip/sw/host $ ./arm-wbregs version 0800010 ( VERSION) : [....] 20190709 which is the correct result. Thanks15:55
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f003brvIs anyone else having trouble using iceprog on newer Mac OSX?17:42
f003brvIt works fine on my older Mac17:42
ZirconiumXf003brv: define "trouble"17:45
f003brvSure, i get this error: Can't find iCE FTDI USB device (vendor_id 0x0403, device_id 0x6010 or 0x6014).17:46
f003brvdespite following this: http://www.clifford.at/icestorm/notes_osx.html17:46
tpbTitle: Project IceStorm Notes for Installing on OSX (at www.clifford.at)17:46
f003brvdoing kentunload for com.apple.driver.AppleUSBFTDI driver does not fix17:46
f003brvtpb: thanks tried it already and works fine on my older Mac as mentioned17:47
adamgreigshould nextpnr use the lut carry-outs properly on ice40? my 64bit adder is kinda slow and the critical path is the entire carry chain from 0 to 6317:48
adamgreignot sure if anything can be done17:49
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f003brvjust checked with lsusb and I see the device too18:05
f003brvis there a support email18:08
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pepijndevos_Does yosys have any useful passes to go from a sea of muxes to more insightful logic?19:57
pepijndevos_I used icebox_vlog to convert a bitstream to verilog, and now trying to make that a bit easier to look at.19:57
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daveshahYou might find that `abc` without any arguments gets you something a bit more useful20:08
daveshah(this will remap to a default set of gates)20:09
daveshahmight need a `techmap; opt` first if it is in `$mux` rather than `$_MUX_` cells20:09
adamgreigis there a convenient way to stick a signal into a black box that stops it being optimised away, besides setting it to a port?20:10
daveshahadding `(* keep *)` might help20:10
adamgreigthanks, i'll have a go20:12
pepijndevos_will try20:16
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pepijndevos_yea, now it has a bunch of actual logic gates... 415 of them20:21
pepijndevos_(also needed a proc)20:21
adamgreigare you doing that ice40 ctf by any chance?20:21
pepijndevos_yea haha20:21
adamgreigenjoy :p20:22
adamgreigi just went from the default icebox_vlog mux output by hand manually20:22
adamgreigit was a bit tiresome...20:22
pepijndevos_A BIT??20:23
adamgreigonce you get the pattern most of them are the same20:23
adamgreigjust have like six notebook pages filled with https://photos.app.goo.gl/u8f8AMse1eJ7Pm72720:24
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pepijndevos_ehhhh, not sure if I'm that dedicated. I was mainly interested in the bitstream part, which turned out pretty trivial because, you know... icestorm.20:25
pepijndevos_Love the notebook though20:26
adamgreigthere are easier, smarter ways i think20:27
pepijndevos_looking at graphiz is probably not it though https://twitter.com/pepijndevos/status/114868796659385139220:28
adamgreigyea that is not super duper informative20:29
daveshahI wonder if cover would be useful here20:30
pepijndevos_Does that do some sort of reachability/testability analysis?20:34
daveshahminimal example - https://github.com/YosysHQ/SymbiYosys/blob/master/docs/examples/quickstart/cover.sby and https://github.com/YosysHQ/SymbiYosys/blob/master/docs/examples/quickstart/cover.sv20:36
tpbTitle: SymbiYosys/cover.sby at master · YosysHQ/SymbiYosys · GitHub (at github.com)20:36
daveshahThis won't help if the bitstream contains any excessively difficult cryptographic functions though20:37
pepijndevos_Might try tomorrow. Not really going to learn much about reverse-engineering FPGAs, but learning more Yosys internals can't hurt either.20:42
adamgreigi definitely considered just running the verilog in a simulator and fuzzing it :P20:43
pepijndevos_Right... but that basically means brute-forcing an 8-char password in a simulator, right?20:44
adamgreigyou might like to hope a smart fuzzer would figure it out quicker, but in this case i don't think it actually would20:45
adamgreigdoing it by hand wasn't too bad though, really20:45
pepijndevos_Looking at that ball of wires, it does not seem to be a simple shift register that compares with the password. I'm guessing some sort of hash function, but maybe I underestimate the explosive growth of low level logic.20:46
pepijndevos_Cover seems fun to try.20:46
daveshahYou might need to try and find the UART clock divider and patch it out for cover to complete quickly enough20:47
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pepijndevos_If the "challenge" is "look at this code with a notebook in hand" I think I'll find something else to do.20:47
adamgreigfwiw that is not the nominal challenge20:49
adamgreigyou can turn the muxes into four-input boolean expressions pretty quickly by hand though20:50
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