Monday, 2019-07-08

*** tpb has joined #yosys00:00
*** gsi_ has joined #yosys00:29
*** gsi__ has quit IRC00:32
*** lutsabound has quit IRC02:32
*** PyroPeter has quit IRC02:43
*** PyroPeter has joined #yosys02:57
*** citypw has joined #yosys03:19
*** indy has joined #yosys03:21
*** citypw has quit IRC03:24
*** citypw has joined #yosys03:32
*** Ristovski has quit IRC04:14
*** rohitksingh_work has joined #yosys04:54
*** promach has joined #yosys04:58
promachCould anyone comment on ?04:58
tpbTitle: asynchronous reset mechanism of D flip-flop in yosys - Page 1 (at
*** citypw has quit IRC05:17
*** dys has joined #yosys05:35
*** rohitksingh_work has quit IRC05:59
*** _whitelogger has quit IRC06:05
*** _whitelogger has joined #yosys06:08
*** promach has quit IRC06:08
*** phire has quit IRC06:23
*** phire has joined #yosys06:30
*** dys has quit IRC07:00
*** emeb_mac has quit IRC07:03
*** [Ristovski] has joined #yosys07:05
*** [Ristovski] is now known as Ristovski07:05
*** cr1901_modern has quit IRC07:20
*** cr1901_modern has joined #yosys07:24
*** GoldRin has quit IRC07:54
*** promach has joined #yosys08:23
*** m4ssi has joined #yosys09:19
*** promach has quit IRC10:25
*** gmc has joined #yosys12:39
gmchowdy folks, i was wondering, how do the a << b operators synthesize with yosys? is that even something yosys does, or is that down to arachne-pnr?12:41
tpbTitle: yosys/techmap.v at master · YosysHQ/yosys · GitHub (at
daveshahthis defines how a shift operator maps to logic12:43
daveshahlater passes in Yosys (e.g. abc) will then map this to LUTs12:43
gmcinteresting, thanks..12:46
gmcnot sure how a for loop would translate into lut's yet though12:49
daveshahThis effectively creates muxes using ?:12:50
daveshahThose muxes are then mapped to LUTs further downstream (usually in the abc pass)12:50
gmci was thinking a case statement, but something along those lines is what i expected12:50
gmc(then again a case would probably become a mux too)12:51
daveshahYes, nothing is mapped directly a LUT - it all goes through intermdiate logic like muxes and optimisation first12:51
gmci'm a bit confused as to how 'buffer = {buffer, (2**i)'b0};' is valid verilog though, but i guess this verilog is somehow special or maybe it is legal in some recent iteration of the standards?13:25
daveshahIt may not be legal - this file is pretty much Yosys-specific anyway13:30
*** GoldRin has joined #yosys13:35
ZirconiumXYou could probably make it legal through something like `buffer = {buffer, {2**i{1'b0}}}`, right?13:37
ZirconiumX(mostly testing my own knowledge of Verilog here)13:38
daveshahYes, that looks more correct13:38
gmci don't think so, i believe the number of repetitions needs to be a constant13:43
daveshahIn this case `i` can be considered constant13:44
gmcsure enough, if i try that it gives a 'error: A reference to a wire or reg (`i') is not allowed in a constant expression.'13:44
gmc(or well, iverilog does anyway, should try that with yosys for good measure)13:45
gmcoh vsim also doesn't like it13:45
ZirconiumXi is not a wire or a reg :P13:48
gmci know that.. you tell iverilog and modelsim that ;)13:48
gmcbut indeed, yosys doesn't complain about it..13:51
gmci'd still like to be able to simulate my hdl before synthesizing though :)13:51
*** vonnieda has quit IRC13:53
*** brasilino has quit IRC13:54
ZirconiumXThat's why we have separate models of cells for simulation14:01
tpbTitle: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at
gmcoh, i did not know yosys did simulation as well!14:04
ZirconiumXIt doesn't, really14:04
ZirconiumXBut you can use this to simulate a synthesized design14:04
*** emeb has joined #yosys14:07
*** vonnieda has joined #yosys14:09
pepijndevos_So what does the sim command do then, if not simulate?14:25
daveshahIt does simulation, but not in the same way as a traditional Verilog simulator14:27
daveshahYosys doesn't process stimuli, the event model, delays, etc14:27
daveshahinstead the sim command allows a simple clock to be specified14:27
gmchmm some other thing i've been trying to figure out with yosys is why gives an error 'Warning: Identifier `\myfoo.BAR' is implicitly declared at implicit.v:35.' and 'Warning: Wire top.\myfoo.BAR is used but has no driver.'14:33
tpbTitle: [VeriLog] module foo #( parameter BAR = 3'b111 )( input [2:0] in, output [ - (at
gmciverilog and modelsim are happy about it, and I think the verilog standard allows it, but then again there's so many standards and i'm new to verilog anyways (used vhdl before)14:33
ZirconiumXgmc: BAR is a parameter, not a wire/reg14:33
gmcok, but if i write 'top_in = 3'b111' it's fine.. once i instantiate a module, isn't the parameter like a constant?14:35
ZirconiumXIt's a constant inside the module, I believe14:36
gmc3'b111 is not a wire/reg either14:36
*** voxadam has quit IRC14:36
*** voxadam has joined #yosys14:36
ZirconiumXI'm pretty sure BAR is out of scope here14:37
gmchmm i was under the impression that you could always access anything in verilog in the hierarchy by walking through the hieracrhy with dot-seperated paths14:37
gmcand iverilog and modelsim think this is fine again..14:38
* ZirconiumX digs out the specification14:38
gmcwhich one? :)14:38
ZirconiumXIEEE 1364-200514:38
gmci was looking at 1800-2009, but hadn't found it yet14:39
ZirconiumXYosys' SystemVerilog support is a bit shaky14:39
gmci used this to synthesize: yosys -p "read_verilog implicit.v; synth_ice40 -top top -blif top.blif" -q14:40
gmcnot sure what the default is, 1364-2005?14:40
tpbTitle: Internal module wires are not accessible using dot notation · Issue #647 · YosysHQ/yosys · GitHub (at
ZirconiumX4.10 Parameters14:40
ZirconiumXVerilog HDL parameters do not belong to either the variable or the net group. Parameters are not variables; they are constants.14:41
ZirconiumXIn other words, it's not a net14:41
ZirconiumXSo if I read this spec correctly, Yosys is correct here and iverilog/modelsim are wrong14:41
gmcinteresting (and a bit disappointing :)14:42
ZirconiumXDo you want to define a constant with a name?14:42
gmcyes, i guess i will need to `define instead of (ab)using parameters for this14:42
ZirconiumXActually parameters are fine for this14:43
ZirconiumXBut you want to use `localparam` here14:43
gmci had that before, but then changed it to parameter because of this implicit definition thing14:43
ZirconiumXFor example, in module top, add `localparam FOO = 3'b111;`, and then you can reference `FOO` in `top`.14:43
daveshahI believe hierarchical references are primarily a simulation feature14:43
daveshahThey might be valid in synthesis in some of the newer SystemVerilog standards14:44
gmcah yes, but I want to define the constant values in the module (in my actual design the module is in a different file and `included)14:44
gmccorrection, i had localparam, but had to refactor to parameter to satisfy modelsim..14:45
*** AlexDaniel has quit IRC14:53
*** AlexDaniel has joined #yosys14:53
corecodehm, i can't pass -p and -s at the same time?15:18
ZirconiumXcorecode: yes you can15:30
ZirconiumXBut -p executes after -s, I believe15:30
corecodedoesn't look like, at least not for my version15:37
ZirconiumXWhich version do you have?15:37
*** m4ssi has quit IRC16:11
*** maikmerten has joined #yosys16:27
*** Jybz has joined #yosys18:04
*** _whitelogger has quit IRC19:14
*** _whitelogger has joined #yosys19:17
corecodecompiled some weeks agin19:51
corecodeoh no, chip simulation works, bitstream doesn't work.  it does run, but not how i expect it to run - only one out of 6 channels has output19:52
*** vonnieda has quit IRC20:03
corecodevery derp.20:04
corecodemcu fail20:04
*** vonnieda has joined #yosys20:04
*** fsasm has joined #yosys20:16
*** maikmerten has quit IRC20:40
*** Jybz has quit IRC20:43
*** fsasm has quit IRC21:37
bwidawskso check_label stuff in the script pass serves as both a sync point as well as bookends for the steps in synthesis you wish to run, is that accurate?22:10
daveshahbwidawsk: primarily, it allows you to use -run label or -run from:to22:11
bwidawskso from a state sense, you can never expect the previous block has run...22:12
daveshahFor FPGA synthesis usually it's fair to say any end user would run all the parts22:13
daveshahPartial runs would only be for debugging22:13
bwidawskdaveshah› thanks22:13
daveshahBut the only state in the script itself should be the options22:13
daveshahAll other state should be in the RTLIL netlist22:13
daveshahIt's fair to assume that a previous block has run at some point in time22:14
daveshahBut the design might have been dumped to a file and loaded again, for example, maybe for debugging22:14
*** vonnieda has quit IRC22:37
*** AlexDaniel has quit IRC23:01
*** AlexDaniel has joined #yosys23:02

Generated by 2.13.1 by Marius Gedminas - find it at!