Saturday, 2019-07-06

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trmmhow much difference is expected between two bitstreams with similar verilog inputs?14:37
trmmFor faster cycle times, is there anyway to ask nextpnr to only use limited parts of the chip (so that more of the bitstream is "empty")?14:37
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trmmmore context: I added faster reprogramming support to tinyprog so that it doesn't erase sectors that it doesn't need to and it seems that many small changes in the verilog leave much of the bitstream identical so there is a definite speedup from the patch14:39
trmmotherwise erasing and flashing the entire chip is around 60 KB/s, so a full bitstream takes about 12 seconds14:41
trmmwith the partial update it can be as fast as the time to read the bitstream, around 600 KB/s for an identical one14:41
cr1901_modernI need to update/play with tinyprog again15:19
cr1901_modernlast I used it was late September to add micropython support15:19
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ZirconiumXdaveshah: Where did the names for the cells come from? I've read through the docs and the ECP5 cells mostly match the docs, but is it just to match the docs?15:59
daveshahZirconiumX: usually either to match the vendor primitives or be obvious that they don't match (any TRELLIS_ or ICESTORM_ primitives)16:01
ZirconiumXAh, okay16:01
daveshahtrmm: region constraints are a bit of a work in progress16:02
daveshahHowever, because of the ECP5 bitstream structure if a design uses a significant number of IO it is likely a large number of frames will change16:02
daveshahBecause of routing through them changing16:02
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corecodei guess i can't use enum with yosys?17:07
FL4SHKcorecode:  SV support is incredibly weak18:19
ZirconiumXcorecode: unless you pony up for Verific18:50
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emeb_macboo who?21:30
ZipCPUWhy are you crying?21:42
ZirconiumXI have absolutely no idea who the best person to ask for this is, but Quartus and Yosys have a disagreement on whether Verilog generate for loops requires blocks to have names21:43
ZirconiumXSo who's right, for the sake of writing portable Verilog?21:43
daveshahI think, at least in plain Verilog, generate blocks have to be named to have wires/regs declared inside them but not otherwise21:44
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ZirconiumXHere's the snippet Yosys accepts but Quartus complains about:
tpbTitle: test.v ยท GitHub (at
ZipCPUZirconiumX: Yosys issues no errors for the block names, so ... I put them in when something has to work with Quartus21:49
ZirconiumXThus why I'm asking which is correct :P21:49
daveshahI think Yosys is correct according to the newer standards but not original Verilog21:50
bwidawskquartus claims to support verilog 2001 and SV 200521:50
bwidawskneither work for me without the name21:50
daveshahistr there are differences in support between paid and free quartus21:50
daveshahThere was a twitter thread about this a while ago21:51
bwidawskI am using paid21:51
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ZirconiumXWhat does Yosys' "public wires" stat mean?22:04
ZirconiumXI/O pins or something?22:05
daveshahWires that weren't created or processed by Yosys (eg without a dollar prefix name)22:05
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