Friday, 2019-07-05

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bwidawskI don't know the architecture well, but you could catch the signal when at a prompt, or let it through while a command is running03:44
bwidawskI'm happy to dig into it if people think the RFC is a good idea03:45
bwidawsktnt, daveshah, ZirconiumX: ^^03:45
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trmmon the ulx3s schematic the FLASH_SCK line is connected to U3, which matches the LPF file.16:40
trmmhowever, nextpnr says:16:40
trmmERROR: IO pin 'flash_clk$tr_io' constrained to pin 'U3', which does not exist for package 'CABGA381'.16:40
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trmmah, I see there is an issue already open about it:
tpbTitle: database for ECP5 CABGA381 is missing pin U3 · Issue #75 · SymbiFlow/prjtrellis · GitHub (at
daveshahFor the flash clock you should use the USRMCLK primitive anyway16:43
daveshahI'm not even sure if Diamond allows you to use the clock as a normal IO or forces you to use the primitive too16:44
trmmERROR: No wire found for port USRMCLKTS on destination cell usrmclk_inst.16:50
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daveshahIs your trellis and nextpnr up to date?16:50
daveshahThis was fixed fairly recently16:51
trmmlast pulled in April, so I'll do an update16:51
daveshahJust updating nextpnr should be fine16:51
daveshahThink I fixed the nextpnr side sometime in may16:52
trmmtrellis was up to date since you just merged my most recent pr.  I'm rebuilding nextpnr now16:53
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trmmIs generating the chipdb bba files supposed to consume all physical memory in the known universe?17:01
tnttrmm: no ... just a few G17:03
daveshahThere was a patch by whitequark recently to serialise building them17:04
trmmfinally made it past the 85k file without triggering the oom.  make -j8 was a mistake in this case...17:05
daveshahThis is exactly what that patch was supposed to fix17:06
trmmok, that fixed the USRMCLKTS issue17:12
pepijndevos_ZirconiumX, PCB has shipped!17:17
ZirconiumXpepijndevos_: and now in a month you'll find out you fucked up17:17
ZirconiumXDid you add a ground plane?17:17
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pepijndevos_ZirconiumX, yes I did. It's all 2 layer through hole stuff, so there is a lot that can be fixed.17:48
ZirconiumXI still think you should learn manual routing17:52
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pepijndevos_I've routed some fairly big 2 and 4 layer PCBs, and it's my least favourite part of electronic design. That moment where you're just staring hopelessly at a giant ratsnest... I'm sure it gets better with experience, I've seen some pretty amazing routing jobs.17:56
daveshahPersonally I find routing quite relaxing17:58
pepijndevos_But for this project the whole point of it is kinda the automation IMO. Ideally I'd just compile directly to PCB. I wonder if nextpnr could help here...17:58
daveshahNo, nextpnr is designed for highly constrained applications (i.e. FPGAs). It would be no good for ASICs let alone PCBs17:59
pepijndevos_I've explained pcb layout to people as connect the dots for grownups.18:00
pepijndevos_So how does ASIC place and route work?18:00
daveshahPlacement isn't that different, just with free choice of location rather than fixex18:01
daveshahRouting I don't know the details but presumably similar enough to a PCB18:02
pepijndevos_But I assume for the amount of transistors in a modern chip there is a lot less manual work than typical PCB layout... or ASIC design is a special kind of hell I don't want to end up in.18:03
daveshahYes, most general ASIC routing is automated afaik18:03
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daveshahBut I suspect some of the standard cells are routed by hand18:04
daveshahthe routing between those cells wouldn't usually be by hand18:04
pepijndevos_So is there any oss asic pnr yet? Or do you feed the yosys netlist into commercial tools?18:05
daveshahYes, there is
tpbTitle: Qflow (at
daveshahI think there was a tapeout of picorv32 with it recently18:06
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trmmThanks for the help with the ecp5 USRMCLK issue. The tinyfpga bootloader now works on the ulx3s board, which is so much faster than the bitbang JTAG20:28
cr1901_modernoh nice!20:31
trmm(The FTDI used by ujprog has only 3 megabaud link and requires sending 16 bytes for every byte of the bitstream, so it is very slow)20:35
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cr1901_modernI'd like to see more direct USB connections to FPGAs even if it's limited to 1.120:37
cr1901_modernerr Full Speed*20:38
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trmmthe tinyfpga-ex has all of the USB-C pins connected. I wonder how well that will work in practice22:09
trmm(or if everyone will just use the USB 2 pins)22:09
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