Thursday, 2019-06-27

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pepijndevos_ZirconiumX, I wonder if it'd be feasible to synthesize some of these things would be more fun than a blinky led.10:45
tpbTitle: countercomplex: Some deep analysis of one-line music programs. (at
ZirconiumXpepijndevos_: Probably, as long as you don't invoke something like sin()10:47
pepijndevos_Lots of 32 bit multiplications get thrown around though, so you'd have to be careful what you select indeed.10:50
ZirconiumXI did look at the 74 series a bit more10:51
ZirconiumXThere were multiplier ICs10:51
ZirconiumXThe '261, '274 and '275, for example10:52
ZirconiumXOr the 284/28510:52
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pepijndevos_Are they still being made though?10:53
ZirconiumXI doubt it :P10:53
pepijndevos_I've been thinking if copy-pasting a booth multiplier from somewhere that uses our adder chips would be better than the xor mess that currently gets generated10:54
ZirconiumXI'm reasonably sure the Booth multiplier is synchronous, not combinational10:55
ZirconiumXYou'd want a Wallace/Dadda tree10:55
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pepijndevos_Ah, probably true. It's been a while since university made us write out logical algorithms.10:57
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pepijndevos_I have a whole list here, but nothing so far that is interesting and small
tpbTitle: avrfreertos/music_formula_collection.txt at master · feilipu/avrfreertos · GitHub (at
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pepijndevos_ZirconiumX, you know what would be usefull... if we could tell yosys to abuse spare pins for otherwise suboptimal arrangements. I currently have a situation where it makes 7 muxes and one and gate which could have been a mux with a fixed input. But I suppose that's just a distant dream...14:34
ZirconiumXHow big are the muxes?14:35
pepijndevos_Uh, in what sense?14:35
ZirconiumXIf I'm truthful here I want to see what happens if you can source '150 16-input muxes14:35
ZirconiumXInput count14:35
ZirconiumXFor example, that works with mux4s but not mux2s14:36
pepijndevos_They are 4x1mux214:36
ZirconiumXThen you can't build an AND gate from it14:37
ZirconiumXI think post-Yosys would need a unification pass, to see which muxes could be merged14:38
pepijndevos_Hrm, then I don't understand what is going on. Never mind then. For one port it has a bunch of muxes and an AND gate connected to the same signals.14:39
ZirconiumXCan you sketch out a diagram?14:39
pepijndevos_Yosys can :) The polarity signal on the left drives these muxes and the and gate which control level on the right14:41
tpbTitle: Imgur: The magic of the Internet (at
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pepijndevos_Basically what I'm trying to do is make something that counts up and down efficiently.14:43
tntpepijndevos_: over how many bits ?14:48
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tntpepijndevos_: I mean up/down counter is really just the adder chip with the A input wired to its output (registered) and the B input wired to a signal with LSB fixed to 1 and all the other bits being the counting direction.14:50
pepijndevos_Right, buuut... ok so what I'm trying to do is make a LED fade in and out. So I have an inner PWM loop and an outer level loop. What I have now works, but I'm tweaking things to reduce chip count.14:53
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pepijndevos_oh this looks promessing14:54
pepijndevos_9 chips, so sexy.14:55
pepijndevos_The sad thing it uses a whole chip for *one* XOR gate, but that seems a fair price for so much awesomeness.14:56
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tntdoes 9 chip also include the actual pwm ? or is it just outputing and N bit value ?  (and how much is N) ?15:00
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pepijndevos_tnt, it does the actual PWM. So there are 4x4 adders that count up a 16 bit number that is stored in 2x8 flip-flops, then there are 2x4 comparators that compare the lower 7 to the upper 7 bits and an XOR on the MSB that switches the polarity of the PWM every other run15:06
pepijndevos_So now updating the Kicad generator to handle the XOR chip, and I should be all set to make the most elaborate useless PCB ever.15:08
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pepijndevos_ZirconiumX, <316:06
tpbTitle: Generate KiCad netlists by pepijndevos · Pull Request #3 · ZirconiumX/74xx-liberty · GitHub (at
ZirconiumXpepijndevos_: That could probably be manually routed, I think :P16:07
pepijndevos_It could be... you could also design it completely by hand.16:08
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pepijndevos_Honestly, I'm not sure the autorouter is good enough to route a RiscV...16:12
pepijndevos_There is an issu on Skidl to support Eagle libraries and netlists, but no actual work towards it I think. Let alone Althium or Orcad.16:13
ZirconiumXpepijndevos_: I think PCB of the gEDA suite has a topological router, but I don't know how good it is16:14
ZirconiumXAs for manual routing; I think that's perfectly fine16:16
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benreynwarHas any tried using removing irrelevant logic from a design before doing formal testing?  I'm having the problem that writing out the VCD trace is the limiting factor.  I thought maybe I could run yosys over the design first to strip out all the logic that can't possibly effect any assert or assume statements, and then run the formal testing on the stripped down version.  Most of the logic (and state) in the design is in the21:59
benreynwardata path, while what I'm really trying to test with the formal testing is the control logic.  Is this a sensible idea, and any suggestions about how I should go about it?21:59
ZipCPUHello, benreynwar!22:03
daveshahbenreynwar: anything sufficiently remote from asserts or assumes should be removed by a call to `opt`, or perhaps even just `opt_clean -purge`, after prep22:03
benreynwarZipCPU: Hi again!22:06
benreynwardaveshah: Thanks for the pointer.  I'm going to go and try to understand what going on behind the symbiyosys scripts and then I expect I'll be back with more questions.22:07
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