Wednesday, 2019-06-26

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pepijndevos_This is so weird... with async reset Yosys breaks my multiplication and then optimizes it away.08:20
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pepijndevos_ZirconiumX, any chance you could commit that comparator pass for me to play with?09:30
ZirconiumXpepijndevos_: yeah, give me a bit09:31
pepijndevos_I think that if that works, the PWM benchmark should be quite compact.09:31
pepijndevos_If I can get that down to a reasonable amout of chips, I think it'd be a good PoC to order that on PCB for the most elaborate fading LED thing ever.09:33
ZirconiumXpepijndevos_: I think the 181 is available in the LS family, but I can't quite tell09:35
pepijndevos_ they know it exists, but don't actually have any in stock09:38
pepijndevos_It also exists in the HC family, but no stock either.09:39
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ZirconiumXpepijndevos_: I pushed my comparator pass in the `cmp` branch10:35
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pepijndevos_ehhhhh, something is messed up11:24
pepijndevos_The upper bits of my counter just synthesize to xxxx11:25
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pepijndevos_ZirconiumX, why did you use the 74HC688_1x1EQ8 for equality but 74HC85_1x1CMP4 for gt/lt? How much did you test this? Output seems pretty wrong. Have to do some actual exam work now, will look another time.11:39
pepijndevos_Oh nvm, the 8 bit does *onl* eq, the 4 bit has more outputs11:40
ZirconiumXpepijndevos_: Because the '688 is an 8-bit equality comparator, while the '85 is 4-bit, but also does greater-than/less-than11:40
pepijndevos_I read the datasheet title and they both said magnitude comparator.11:40
pepijndevos_Seems like for my 8 bit word, only 1 4 bit comparator gets generated :/11:41
ZirconiumXpepijndevos_: ABC is pretty good at optimising equality operations, so I don't actually use it11:41
ZirconiumXUse the '68811:41
ZirconiumXBleh, you can figure out what I meant11:41
pepijndevos_ZirconiumX, ahhhh, I think WIDTH is incorrect? Y_WIDTH is always 1. Can you do something like max(A_WIDTH, B_WIDTH)? I'll have to think about how to handle uneven lenghts...11:47
pepijndevos_(what does this magic $pos line do)11:48
ZirconiumXUpconverts a smaller signal into a bigger signal11:48
ZirconiumXpepijndevos_: try this patch
tpbTitle: [Diff] diff --git a/74_cmp.v b/74_cmp.v index 63c463a..5bd17c9 100644 --- a/74_cmp.v - (at
pepijndevos_Ah, so that handles when A_WIDTH != B_WIDTH11:50
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pepijndevos_ZirconiumX, Definitely an improvement, but it appears only to look at one bit of the counter
tpbTitle: Imgur: The magic of the Internet (at
pepijndevos_unless I understand the syntax in the block wrong11:55
pepijndevos_ahhh, I think I know11:55
pepijndevos_Need to replace Y_Width with max_width in a few places11:56
ZirconiumXThough I managed to produce a bug in Yosys11:56
ZirconiumXI think?11:56
ZirconiumXdaveshah: should be reported as a bug?11:57
tpbTitle: ERROR: Found error in internal cell \axilxbar.$lt$../benchmarks/axilxbar.v:1435$ - (at
daveshahThis is almost certainly a problem with how you are using `$pos`11:58
daveshahYosys has various checks to make sure the contract of its internal (dollar-prefixed) cell types aren't violated11:58
ZirconiumXAh, I see11:59
* pepijndevos_ has no idea what's going on with $pos at all11:59
daveshah`$pos` just does with conversion, with sign extension if applicable otherwise zero extension12:00
daveshah*width conversion12:00
tpbTitle: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at
pepijndevos_Ah, fixed it12:02
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ZirconiumXpepijndevos_: <--- this probably looks like your patch12:04
tpbTitle: diff --git a/74_cmp.v b/74_cmp.v index 63c463a..19020d8 100644 --- a/74_cmp.v - (at
pepijndevos_exactly :)12:05
pepijndevos_PWM with my reset changes would be less than 10 chips now!!12:05
pepijndevos_So question is... which parts should be used? Comparison definitely makes my example a lot smaller.12:08
pepijndevos_At least I don't think I'll need to make a PR for my changed to cmp as yours are identical :)12:09
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pepijndevos_Probably worth looking closer at equality to see why it's not as efficient. My guess is a lot of 1-bit comparisons that use a full chip.12:11
pepijndevos_Ok, I should really start studying. Looking forward to pull everything together after my exam tomorrow.12:12
ZirconiumXpepijndevos_: As I mentioned, it's because ABC is much better at optimising equality tests12:19
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pepijndevos_ZirconiumX, can't be much more efficient than a single chip, right? Or you mean optimizing all stuff around them? Yesterday you had some idea about variables being much more costly than constants, which seems to be the case. Can detect that and fail the techpass?12:46
ZirconiumXpepijndevos_: Yes, it can be more efficient than a single chip12:46
ZirconiumXSingle bit equality tests can be XOR gates, which you can fit four in a chip12:47
pepijndevos_Right. So the trick is to gate the techpass for wide comparisons (on variables)?12:48
ZirconiumXWhich I try to do12:48
pepijndevos_Oh yea, I see... and what about the variable part? I only see a fail on width, but no idea if we can even access than info.12:50
ZirconiumXWe can, I believe12:50
ZirconiumXI think techmap sets CONSTMSK12:50
ZirconiumXBut I'll go check12:50
pepijndevos_Oh sweet12:51
ZirconiumXYeah, there's _TECHMAP_CONSTMSK_12:52
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pepijndevos_(as obvious to everyone, running cadence through double X11 forwarding and a VPN is not fun at all)12:52
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pepijndevos_ZirconiumX, I'm trying something like wire _TECHMAP_FAIL_ = (A_WIDTH <= 6 && B_WIDTH <= 6) || _TECHMAP_CONSTMSK_A_ == 0 || _TECHMAP_CONSTMSK_B_ == 0; which always fails it seems.14:11
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ZirconiumXpepijndevos_: What are you using as your benchmark?14:21
pepijndevos_ZirconiumX, various processors. Picorv32 and VexRiscv at the moment.14:23
pepijndevos_But I'm not 100% convinced I got my parameters and conditions right. Verilog seems to be very loose with its types, VHDL would kill you if you compared a bitmask to a number like that.14:24
tntpepijndevos_: numbers in verilog are 32 bits unsigned IIRC.14:25
pepijndevos_So uuh, is there an equivalent to {any <= '0'} or something like that? Like, whatever this is, tell me if it's all zeros.14:26
tnt== 0 ?14:27
pepijndevos_Ok great14:28
tntyou could also use assign is_x_zero = ~|x;14:28
pepijndevos_whoa, that's a funky operator.14:29
tnt~  is NOT   |x  ORs all the bits of x together.14:29
pepijndevos_lol, nice. Do all unary bitwise operators work like that?14:30
tntyeh you can ^x  or &x ...14:30
pepijndevos_ZirconiumX, I think I got it sorta working.14:36
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pepijndevos_It uses exactly one EQ8 in both VexRiscv and Picorv32, but it actually improves chip count at least.14:37
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pepijndevos_Ok, *another* PR sent. Studying is going well today XD (I'm running simulations in the background)15:00
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* ZirconiumX pokes pepijndevos_ 19:27
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pepijndevos_ZirconiumX, eh?19:55
pepijndevos_Oh, stuff has been merged. Cool :)19:56
pepijndevos_ZirconiumX, I just pushed an update to the kicad branch that lets me compile pwm256.v to 5 chips and get them in KiCad.19:57
pepijndevos_oh derp, I'm an idiot... how does this even work haha19:58
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pepijndevos_I'm thinking that if things work out, I could make an actual PCB over the weekend.20:08
pepijndevos_That would be so cool20:08
ZirconiumXYeah, it would20:10
ZirconiumXPut my name on there somewhere, too, would ya?20:10
pepijndevos_Would you like ZirconiumX, Dan Ravensloft, or something else? (send me SVG? haha)20:11
pepijndevos_Also, I'm starting to think that if you'd write a RiscV with 74xx in mind, it would be waaaay less chips.20:12
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pepijndevos_I wonder if I can modify the pwm to fade in and out and synth to 10 or less chips. Then I just have to add a clock and LED to make a breathing LED.20:19
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ZirconiumXpepijndevos_: ZirconiumX is fine20:54
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benreynwarHi all!  I'm playing with symbiyosys for the first time.  Is it normal that "Writing trace to VCD file: engine_0/trace.vcd" can take over an hour for large designs?  Running the BMC only took 2 minutes since it failed at step 7 but I haven't managed to actually get a failing trace yet.22:05
ZipCPUbenreynwar: Wow!  Not sure I've ever tried SymbiYosys on a design where it took that long to write a VCD file22:14
ZipCPUIn general, I'd advice running on a smaller design if possible22:14
ZipCPUStill, that's a new one for me22:14
benreynwarzipcpu: Yeah!  I started off with a small submodule yesterday and it all went smoothly, so today I thought I'd try the top level :).22:16
ZipCPUAhm ... how big is this top level design?22:16
* ZipCPU has never applied formal to an entire design22:17
ZipCPUNormally, I break a design up into smaller pieces to formally verify it22:19
benreynwarI've set all the generics to small values so that it'd only take a couple of thousand LUTs on an FPGA.22:19
ZipCPUWell ... I have applied formal to a couple thousand LUTs before ...22:19
ZipCPUOne of the crossbars I applied formal to required nearly 3k iCE40 LUTs22:20
ZipCPUbenreynwar: Can I try your design myself?  See if I have the same problem?22:21
benreynwarIt's a work project, so I'm afraid I can't share the code :(.22:22
ZipCPUI can understand22:22
ZipCPUSymbiotic EDA does sell support contracts22:23
benreynwarYeah, I should look into that.  I'm using the trial license at the moment (the design is in VHDL) and am trying to get a feel of how useful formal is for our designs.22:26
ZipCPUSo, what I normally do ... I normally verify all of the "leaf modules" within the design22:27
ZipCPUThat is, I verify any/all of the bus masters and bus slaves22:27
ZipCPUSeparable components if you will22:27
ZipCPUI then simulate the rest22:27
ZipCPUI'm just now getting to the point where I can formally verify an interconnect--I just haven't tried my formally verified interconnect within any of my designs22:28
benreynwarI wonder if the fact that it's in VHDL could be affecting the trace dumping.22:28
ZipCPUWow ... I hadn't thought of that22:28
ZipCPUIs it spilling information to a file during all this time?  Can you use "trace -f" to see where it's at?22:28
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benreynwarThe header of the trace.vcd gets written where all the signals are defined gets written, but none of the content.   The logfile.txt in the engine_0 folder is empty.22:30
benreynwarThe small design I worked on yesterday worked without any problems though.22:30
ZipCPUWhat solver are you using?22:31
benreynwarI think your suggestion of working on the submodules is the right direction to go.  Then if it is a problem with the VHDL I should see the same issue in one of the submodules.22:31
benreynwarsmtbmc boolector22:31
ZipCPUThanks ... that doesn't help though, since I haven't had any problems with boolector22:32
ZipCPUI have had problems with some of the non-smt solvers, but boolector has been one of my mainstay's22:32
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benreynwarSo I'm going to leave this process running in the background to see if it ever writes than trace file, but move onto testing the submodules individually. As always, thanks for all your help!22:36
ZipCPUI just wish I could've helped more, and perhaps even solved your problem22:36
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