Saturday, 2019-06-22

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pepijndevosZirconiumX, currently the muxes are defined in both the library and as a techmap. Can one of them go?07:12
pepijndevos../74_models.v:12: Module 74AC151_1x1MUX8 was already declared here: 74series.v:14107:12
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pepijndevosAwesome, I got my synthesized 74xx counter to simulate07:23
pepijndevosNow trying to hunt down where ZirconiumX got these benchmark files and see if they have easy to add testbenches.07:30
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ZirconiumXpepijndevos: no; techmap needs them to map large muxes, and ABC can synthesise functions out of muxes, too07:36
ZirconiumXOh, you generated a model from the liberty file07:37
pepijndevosExactly, so the generated model is conflicting with the techmap07:37
ZirconiumXSo remove the generated model :P07:37
pepijndevosBut I need all the other ones.07:38
ZirconiumXDo you?07:38
pepijndevosWhat I think is more sane is to load the liberty file in the script and remove them from models.07:39
ZirconiumXOne question is whether the liberty models are black boxes or not07:39
pepijndevosdepends how you load them. read_liberty -lib makes black boxes07:39
pepijndevosSo these can then be omited from 74_models.v07:40
ZirconiumXOkay, I'll try to make a model for things like the 7428307:41
pepijndevosHold on... I'll try if this works and send a pr so you can see what I'm doing07:41
pepijndevosno need to rewrite all the things just yet.07:41
pepijndevosHuh, I just plainly deleted the models from 74_models.v and it does not even complain.07:45
pepijndevosI don't think it's using those muxes07:47
ZirconiumXIt is, as far as I can tell07:48
ZirconiumXBut presumably it's synthesising the model from the liberty file07:49
pepijndevosYea, but I think the mux techmap is not generating any. If I completely omit the models.v it complains it's missing the adder, but if I removet the verilog mux def it's still happy.07:50
pepijndevosAnyway, pushing changes07:51
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pepijndevosZirconiumX, do you want my simulation stuff too? (possibly in a new branch/pr)07:54
ZirconiumXSure, I'll take a look07:54
pepijndevos thats just the liberty stuff07:55
tpbTitle: Remove duplicate models by loading the liberty ones by pepijndevos · Pull Request #2 · ZirconiumX/74xx-liberty · GitHub (at
pepijndevosI only have a very simple simulation now, trying to find something more interesting and elaborate.07:56
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pepijndevosHrm, the bram doesn't have a verilog model either obviously...09:07
pepijndevosCommenting out that pass, I can run the picorv32 testbench, but it's not working correctly.09:07
pepijndevosZirconiumX, I've been staring at gtkwave to find the difference between the original simulation and the synthesized one and... I have no clue what is going on. Things seem to be not initialised and spread XXXXX like wildfire.09:33
ZirconiumXI've just been trying to synthesize things, but apparently I didn't test it properly too.09:34
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pepijndevosThis seems a reasonable observation ;)09:49
pepijndevosGlad this came to light before you order PCB's for your 1k chips riscv CPU ;)09:50
pepijndevosHonestly, it might be a better idea to write some tests than try to debug picorv32.09:53
pepijndevosIIRC there are various types of DFF with reset and initial values and stuff. Maybe one of those is broken.09:53
pepijndevosI'm going to add more stuff from yosys-bench that has verilog testbenches, which are a whole 4 tests.10:01
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pepijndevosZirconiumX, I've added a bunch more simple benchmarks, which should help pin down the problem.10:24
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pepijndevosIn particular cic5 is pretty simple and also turns into XXXX pretty quickly.10:24
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pepijndevosdspmac also produces xxxx10:26
ZirconiumXpepijndevos: file an issue, please10:31
pepijndevosSure. I'll spend a bit more time trying to figure out what is going on, and make a nice issue. So far I've just been piling commits onto the PR.10:33
ZirconiumXI'll review them when I get back from the shop10:35
pepijndevosAt this point I'd be really happy if Icarus could treat an X value as an error and tell me where it happened.10:42
ZirconiumXThe most boring approach is to go through the Yosys script one command at a time and write_verilog10:49
pepijndevosThis might be a very good idea, because the end result is... not okay.10:52
pepijndevosBasicallly there is nothing left except the output DFF.10:52
pepijndevosSuch optimize, many efficient, wow10:53
pepijndevosThe final opt pass deletes everything :/11:06
pepijndevosAhhh... I think I know... it is totally my own fault... maybe11:12
pepijndevosYAY it works... at least I'm getting *something"11:30
pepijndevosYea, it's definitely not correct yet. But... it does stuff, so that's an improvement.11:32
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pepijndevoswelp... I'm not convinced I got the order of the mux pors right...12:45
pepijndevosyea... my muxes are still broken.12:46
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pepijndevosBasically $_MUX4_ has a different idea of what things mean than 74AC153, and I know neither...12:51
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pepijndevosZirconiumX, unless I'm being thick, your S0-S2 seem reversed from the datasheet?13:01
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ZirconiumXAh, possibly?13:03
pepijndevosOk, dspmac works now13:06
pepijndevosBut that's not using mux813:06
pepijndevosPicoRV32 works!!!13:07
ZirconiumXHow many chips?13:10
pepijndevosOh, not sure. Will check.13:10
pepijndevosDidn't change that part though.13:10
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pepijndevosOh, I disabled bram though, because it doesn't have a verilog model, so that's going to be lots of extra memory chips I guess13:11
pepijndevosIf I reenable the pass it makes IDT7132: 813:14
ZirconiumXBRAM is a pretty major optimisation13:15
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pepijndevosAs in... to-be-optimised? Pretty minor difference in chip count at least in the picorv3213:16
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pepijndevoshuh... I'm confused13:17
pepijndevosit seems to add the IDT chips, but does not remove and others13:17
pepijndevosLike... if I comment out "memory_bram -rules ../bram.rules" I get 8 *less* chips.13:19
pepijndevosThat seems broken...13:19
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trmmIs there a way to enable pullups on a ECP5 bidirectional pin with the TRELLIS_IO?14:37
trmmecp5/cells_sim.v doesn't have a pullup parameter, and I'm not sure where else to look.14:37
daveshahUse the PULLMODE attribute either on the TRELLIS_IO or in the LPF14:37
daveshah`(* PULLMODE="UP" *)` or `(* PULLMODE="DOWN" *)` as an attribute14:38
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trmmAh, I had seen that used in non-LPF programs to assign pins. Is that a long-term feature or a transitional one?14:49
daveshahEverything should really be LPF now14:59
daveshahthe attributes were a hack before I got round to writing a LPF parser15:00
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trmmIt would be nice to have pullups selectable in the verilog so that the LPF can be shared between projects that might have different pullup requirements.15:17
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pepijndevosZirconiumX, any prefs what I write the KiCad stuff in? Since it's s-expr based, I'm thinking about Clojure(Script), but if you prefer Python(already used) or something else, no problem.17:42
ZirconiumXI can't speak s-expr, sadly17:47
ZirconiumXNot for lack of trying17:47
ZirconiumXI'd prefer Python17:47
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ZirconiumXI'm having issues getting Yosys to infer a (6-port) block RAM22:30
ZirconiumXIt handles 3-port just fine22:31
ZirconiumXBut I need 622:31
mwkwhat... what kind of hardware actually has a 6-port block RAM?22:33
ZirconiumXWell, I need two pairs of two read/one write ports22:34
tpbTitle: [VeriLog] module sh4a_regfile( input clk, input reset, output [31:0] prog - (at
ZirconiumX(it's a superscalar core)22:34
edwinbalaniA Super-H SH4 one, by any chance? :-)22:35
ZirconiumXedwinbalani: Yep22:35
ZirconiumXStrictly an SH4a which has a few extra instructions and a longer pipeline22:35
ZirconiumXIt's a little painful when Yosys can't infer the RAM though; it's 300 cells for the 3-port and 9,000 cells for the 6-port22:37
daveshahThere's no way that can map to ECP5 hardware22:39
daveshahECP5 BRAM has a max of two write ports, and they have to be shared read write ports in that case and Yosys doesn't even support that22:39
ZirconiumXVague target is a Xilinx chip rather than an ECP5 (though the latter appears to be a bit easier to obtain?)22:41
daveshahXilinx have similar constraints, two write ports are only possible in the form of shared read/ write ports22:41
ZirconiumXAnyway, what are my options here, then? Two copies of the register file?22:41
ZirconiumXSynchronising them would be painful though22:41
daveshahThat allows you to gain read ports but not write ports22:42
daveshahYosys will do that transformation already22:42
daveshahBut obviously not for write ports where it would not match the design22:42
ZirconiumXSo I have to accept the major gate loss for this?22:43
ZirconiumX(I'm being paid for writing this, at least)22:44
mwkyou could try to bump the clock rate for memory ×2 and double-pump a port22:44
mwknot exactly pretty, but then implementing a three-port memory out of simple flops doesn't end well either22:45
ZirconiumXI have no idea if the DRAM/BRAM/whatever can run fast enough22:46
sorearthere’s a XOR trick for synthesizing write ports22:46
ZirconiumXSH4 ran at 200MHz, so this register file would need to be 400MHz22:46
sorearpoke azonenberg, he did this22:47
ZirconiumXSo, my options are pretty limited here22:49
ZirconiumXI'm presuming building a RAM out of DFFs is going to be fairly slow22:49
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azonenbergDid someone say multiport register file?22:52
ZirconiumXazonenberg: I'm the one sorear summoned you for22:53
ZirconiumXI've been commissioned to make a SuperH SH4a core for emulation purposes22:54
ZirconiumXHowever, the SH4a is two-way superscalar22:54
ZirconiumXWhich means I need multiple write ports22:55
azonenbergSo, multiple read ports is obviously an easy problem22:57
azonenbergjust replicate the array22:57
ZirconiumXsorear linked an interesting paper, and said you could help22:57
ZirconiumXYosys can do that already22:57
azonenbergYeah so as far as multiple write ports, the method i've preferred most is probably the paper sorear linked23:00
azonenberglaforest's paper on XOR based multiport memory?23:00
azonenbergif not, that's the method i suggest23:00
azonenbergArea scaling is O(W(W+R))23:00
azonenbergor O(W^2 + WR)23:01
azonenbergSo write ports are expensive and read ports comparatively cheap23:01
ZirconiumXI hopefully only need two of them right now23:01
daveshahGiven this is only 32 deep, I do wonder if LVT would be more efficient here23:05
azonenbergin my case i was going with a multithreaded design23:06
azonenbergso i had 32 regs * 32 threads23:06
ZirconiumXThere are more registers in SH4, but I haven't figured out where I wanted to put them23:06
azonenbergi used a full block ram for each bank of reigsters23:06
daveshahAt 32x32 it's marginal whether DRAM or BRAM would be the better choice23:07
azonenbergI have not done a superscalar processor that was not also multithreaded so i can't suggest much there23:08
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sorearZirconiumX: so how complete is this supposed to be, does it target cycle accuracy, will it be public, and language of choice?23:30
ZirconiumXYes, yes (license yet to be determined, but open source), Verilog23:31
ZirconiumXNot very for the completeness at the moment23:32
sorearZirconiumX: I’m wondering if you just bit off a project larger than the multi person multi year (architecturally sh2 compatible but slower, single issue)23:32
ZirconiumXI'm not being paid to finish this, I'm being paid to start it :P23:33
ZirconiumXAnd yes, I'm aware of the J223:33
ZirconiumXBut byuu managed to perfectly emulate the SNES23:36
ZirconiumXA CPU is a bit less complicated than a game console, even if it is more recent23:37
ZirconiumXI'm reading LaForest's paper and slides, but I still don't think I quite get how the LVT itself is made23:42
sorearhaha. good luck with that, honestly23:44
daveshahaiui, the LVT is small enough that a bit blasted dual write port RAM would be fine23:45
daveshahIt is only 32 entries23:45
daveshah1 bit each23:45
ZirconiumXAh, I think I just grokked it23:45
ZirconiumXThough I'm not smart enough to figure out how to synthesise a PLL or whatever for the double clocking23:46
ZirconiumXI think I can figure out how to divide a clock through a counter, but not multiply it23:47
sorearmaybe you’ll have a MMU public before them23:47
ZirconiumXWell, the j-core website appears to be down, so I'm in no rush23:48

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