Friday, 2019-06-21

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ZirconiumXABC has such wonderful error messages when you mess up the Liberty file15:36
tpbTitle: 25.1.1. Executing ABC. Running ABC command: /yosys-abc -s -f (at
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ZirconiumXdaveshah: What's the difference between a $eq and $eqx cell?17:05
ZipCPUZirconiumX: Try running "help $eqx+" and "help $eq+" within yosys17:07
ZipCPULooks like the difference is "==" for $eq, and "===" for $eqz17:08
ZirconiumXSo $eqx includes don't-care cells17:09
ZirconiumXOr, well, 4-state17:09
ZipCPUYou could argue that they both do, they just do different things with them17:09
ZirconiumXI think it's more correct for me to override $eq cells rather than $eqx cells17:10
ZipCPUIt would help if you only had one type17:10
ZirconiumXBecause I'm not smart enough to know the implications of trying to compare don't care values for equality17:11
ZirconiumXApparently adding equality comparators is a fairly significant loss. Wonder what I messed up.17:43
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daveshahThe problem at the moment is that ABC doesn't optimise around hard blocks17:59
daveshahA lot of the equality optimisations early on are probably significantly optimised by ABC when mapping as soft logic18:00
daveshahThis is lost when you start to map things to hard blocks18:00
ZirconiumXYeah, that's understandable18:05
ZirconiumXBut comparison is a bit harder to optimise, right?18:08
pepijndevos\me waves at ZirconiumX and daveshah19:01
ZirconiumXForward slash, not back19:01
daveshahHi pepijndevos!19:01
ZirconiumXBut yeah, hello19:02
* pepijndevos facepalms19:02
ZirconiumXI'm the crazy person trying to get Yosys to synthesise for 7400 logic19:03
pepijndevosAnd I'm the crazy person cheering you on and playing with it instead of studying for my exams ;)19:06
pepijndevosIt is not entirely unlikely that the majority of my summer holiday will be spent getting to the point where I can build a CPU in VHDL.19:07
ZirconiumXpepijndevos: You should really do your exams, let me be the one who wastes their summer holiday19:10
ZirconiumXI have entirely too much of it19:10
pepijndevosOh, don't worry, my exams will be fine if I don't study in all the weekends and evenings.19:12
pepijndevosThoug I'm very curious how you can have too much holiday. The list of projects I want to do is almost endless, and some of them would take years. Or have...19:13
ZirconiumXIt's too much when you start going stir-crazy about halfway through19:14
pepijndevosHum, as long as I remember to go outside and talk to some friends it tends to be fine for me.19:15
ZirconiumXMy friends are pretty far away19:16
pepijndevosHrm. That sucks. I kinda have this problem a bit too because at the university I pretty much made friends with the foreigners because they seemed more motivated than the dutch guys, but they all go to their parents for the summer.19:18
pepijndevosTalking about dutch... why is the chess program on your github called dorpsgek?19:20
ZirconiumXBecause it behaves precisely as it is named :P19:20
ZirconiumXAnd also a classically British self-deprecating humour joke19:21
pepijndevos... so can I ask if you are a brit who speaks dutch or a dutchy who likes british humor?19:23
pepijndevosAre you are a brit who speaks dutch or a dutchy who likes british humor? :P19:23
* pepijndevos facepalms19:24
ZirconiumXToo easy, pepijndevos.19:24
ZirconiumXI'm a Brit, but while I can't speak any other language, I do have an interest in language in general19:25
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ZirconiumXIt helps that I have a lot of friends from across Europe19:29
pepijndevosWhile I'm eating my dinner, I'm trying to decide what's more fun, get this counter extraction pass to work, make GHDL work, or generate a KiCad netlist.19:30
ZirconiumXI think the counter extraction pass would need to be more general to properly work with e.g. '161s19:30
pepijndevosGeneral in what sense? Except that it only counts down...19:31
ZirconiumXBeing able to count up would be one useful case of it being more general19:32
pepijndevosCertainly XD19:33
pepijndevosSeems kiiinda doable to implement though. But maybe not very important right now. It's just that I want my CPU to have a stack, so a counter seems the way to go.19:34
ZirconiumXWell, a program counter would be a useful place for a '16119:35
pepijndevosYea, but having an adder and dff is not the end of the world for now.19:36
pepijndevosI think the KiCad netlist is the more rewarding thing to try, so you can actually implement your designs.19:38
pepijndevosWhat is your end goal with this project actually?19:42
pepijndevosIf there is such a thing...19:42
ZirconiumXpepijndevos: I'd like to build a RISC-V CPU, but I realise how infeasible that would likely end up being19:43
pepijndevosHave you done any back-of-the-envelope calculations on the theorectial minimum number of chips you'd need?19:44
ZirconiumXA handful, and the answer is "quite a lot", but I'm no 74xx expert19:45
pepijndevosI'm trying to figure out how much chips the original 74xx computers had19:48
pepijndevosand failing...19:52
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daveshahHave you seen SERV? It's a bit serial RISC-V19:59
pepijndevosHmmm, Yosys can generate a Spice netlist. What does it take to simulate that?20:00
daveshahSPICE models for the cells you've mapped to and a suitable simulator20:01
daveshahThere's an example using ngspice here:
tpbTitle: yosys/examples/cmos at master · YosysHQ/yosys · GitHub (at
pepijndevosHmmm, fascinating. I think I found a 74xx spice library somewhere, so with a bit of renaming that might not be too hard.20:05
pepijndevosWarning: no (blackbox) module for cell type `\74AC16373_16x1DFF' (blinking.$auto$$53) found! Guessing order of ports.20:05
ZirconiumXHuh, never gotten that error before20:08
ZirconiumXWell, warning20:08
pepijndevosI get that when generating spice. Probably same for generating low-level verilog? So I suppose models of all the cells are needed for simulation.20:09
ZirconiumXI would assume so, yeah20:09
pepijndevosWould be kinda... useful to simulate in various way before I go and order a PCB hehe20:10
ZirconiumXFair warning, I tend to switch between tasks a lot20:10
pepijndevosSounds not unfamiliar...20:11
pepijndevosI'll continue playing tomorrow and send PR's if I get anything useful.20:12
ZirconiumXSure thing20:12
pepijndevosWhat would be nice is if Yosys could generate Verilog from the liberty code...20:20
pepijndevosOh, it can20:24
pepijndevosread_liberty blah.lib write_verilog blah.v and boom20:24
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pepijndevosAlso maybe relevant:
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