Wednesday, 2019-06-19

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promachhave anyone experienced "loop warnings" yosys LTP command ?04:36
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trmmthanks, dave.  the orpsoc example is very relevant since I'm trying to get the SDRAM on the ulx3s to work and that's exactly what the BIDIR pins are doing.12:35
trmmI'm a little uncertain about the clocking on the SDRAM -- it looks your orpsoc is using the system clock for the SDRAM, although my reading of the data sheet suggests that the SDRAM should be clocked with a 180-degree out of phase clock12:36
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trmmsince the fpga is all positive edge clocked and the sdram is also positive edge clocked, it seems that this would cause the transitions to happen when the sdram expects the inputs to be stable.12:37
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ovfmacro evaluation order seems to differ between yosys and icarus: . i don't have an opinion yet on which is correct or even why would anyone write code like this.22:23
ZirconiumXdaveshah: Don't know if you're awake, but I found a Verilog module where I've got leaking $_DFF_PP[01]_ cells22:24
daveshahZirconiumX: they would be flipflops with an async set or reset22:26
ZirconiumXSo I need to find/define a cell that has those?22:27
daveshahYes, once you do that dfflibmap should map them22:28
daveshahIf you don't care about strict correctness, async2sync will turn them into soft logic and a normal DFF22:29
daveshahThis will break any design relying on actual asynchronous behaviour though22:30
ZirconiumXI'm not entirely sure about how correct my existing designs are, though22:30
ZirconiumXWith `async2sync`, Yosys can turn a 6502 core into ~400 chips22:35
daveshahIncidentally, I think the default for abc is to optimise for delay rather than area22:38
ZirconiumXI did consider including delay information22:38
daveshahPassing -D 100000 to abc should cause it to optimise almost entirely for area instead22:38
daveshahor some other arbitrary big number22:38
ZirconiumXThe AC family is a bit limited22:40
ZirconiumXFast, but limited22:40
ZirconiumXdaveshah: synthesis results appear to be identical for using -D 100000 versus not22:42
ZirconiumXProbably because I didn't add any delay information22:42
daveshahYes, it might be optimising for area in any case then22:42
ZirconiumXI should probably add delay information, though, right?22:43
daveshahYes, I'm not very familiar with the liberty format though22:44
daveshahI think you can even model things like drive strength and capacitance to get an idea of delay vs fanout22:44
daveshahIntended for ASIC cells but should have some relevance to discrete chips too...22:45
ZirconiumXOne thing the 74151 has is an inverting output22:45
ZirconiumXI haven't looked into it much, but is there a way of telling Yosys "can you try doing an inverted mux too to see if that logic is easier?"22:46
daveshahNo, not easily22:46
bwidawskHas anyone done any work on documenting the quality differences on the generated bitstreams of diamond vs. yosys/nextpnr/trellis?22:46
ZirconiumXFailing that, can you pattern-match a mux followed by a not gate?22:47
daveshahZirconiumX: there is the pmgen framework for building pattern matchers in Yosys22:47
daveshahBut it's not that easy to use22:47
daveshahbwidawsk: I haven't done much experimentation, but usually yosys/nextpnr is about 30% behind22:48
bwidawskin what, number of LEs used?22:48
daveshahBoth number of LEs and Fmax22:49
bwidawskdaveshah› I'd really like to know how I can take those measurements myself, any help advice would be very much appreciated22:49
bwidawskI'm happy to post what I find publicly22:49
daveshahHave a look at the log output for both, in particular the number of LUTs (after synthesis) of SLICEs (during pnr)22:50
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daveshahTiming is a bit harder particularly with Diamond you will need to search around a bit for the clock constraint that gives the best Fmax22:50
bwidawskdaveshah› is it scritable?22:50
daveshahnextpnr is, Diamond is a bit harder22:51
bwidawskif you know off the top of your head what to grep, would you be so kind to share? If not, I can figure out22:51
daveshahYou could probably look at this script for inspiration on how to script Diamond22:51
tpbTitle: prjtrellis/ at master · SymbiFlow/prjtrellis · GitHub (at
daveshahI don't have anything readily available grep wise for Diamond though22:51
daveshahIt should be fairly obvious. For timing you'll probably need to look at the twr timing report diamond generates22:52
bwidawskdaveshah› thank you22:52
bwidawskdaveshah› oh, did your last statement imply you had something grepwise for yosys?22:53
daveshahIt doesn't do area but might help with runtime and Fmax22:54
tpbTitle: nextpnr-bench/ at master · YosysHQ/nextpnr-bench · GitHub (at
bwidawskdaveshah› thanks a bunch22:54
daveshahno problem22:55
daveshahInterested to see what the results are22:55
bwidawskas a software person... I'm very ignorant, what's in between blicky, and like a risc-v core in terms of complexity?22:55
daveshahSome of the smaller processor cores are quite interesting22:55
daveshahLike j1a, a forth processor22:56
* bwidawsk nods22:56
bwidawskdaveshah› do you happen to know if there is any hope of acheiving the same data with vivado, or quartus? I've looked at quartus and couldn't really get much out of it22:57
bwidawskwell, and I suppose much of the pipeline isn't done with open tools, as well22:57
daveshahYes, definitely. But check the EULA because some tools don't allow public benchmarking (I think Diamond is fine)22:58
daveshahBoth Vivado and Quartus have Tcl APIs that can be scripted22:58
daveshahThere should be some examples out there of command line flows for both22:58
bwidawskI just couldn't get quartus to dump much that seemed interesting, but I can't say I tried too hard22:58
ZirconiumXbwidawsk: I've been using a 6502 core which seems to be about halfway between the two22:59
ZirconiumXFor even picorv3222:59
daveshahAt least in Vivado there are loads of report_ Tcl commands for this kind of thing22:59
daveshahe.g. report_utilization22:59
bwidawskI'll take another look after I generate something with diamond, which seems more tractable given that you've actually done it :-)23:00
bwidawskZirconiumX› thanks23:00
tpbTitle: GitHub - Arlet/verilog-6502: A Verilog HDL model of the MOS 6502 CPU (at
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