Monday, 2019-06-17

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ZirconiumXdaveshah: (hi, yes, I'm back) Is the $lut cell always for constant values?19:14
daveshahZirconiumX: yes, it is, although I'm not sure whether it appears unless you map to LUTs (either using `abc -lut` or some other method)19:26
daveshah`$shiftx` is usually used for both non-constant values, and also for LUT-style structures even with constant values following the frontend19:27
ZirconiumXI'm just wondering how best to utilise things like muxes19:27
ZirconiumXSince the 74 series has 16:1, 8:1, 4:1 and 2:1 muxes19:27
ZirconiumXabc seems to handle the 2:1 and 4:1 muxes19:28
daveshahYou probably want to use the `pmux2shiftx` command shortly after initial optimisations (before synthesis), and then techmap suitable `$shiftx`s19:28
daveshahEddie has been working on something like this for the Xilinx muxes19:29
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daveshahActually, letting the default techmap rules map `$_MUX_` cells, then using `muxcover` to combine them to larger `$_MUX(4|8|16)_` cells, then techmapping those cells, is probably the path of least resistance19:33
ZirconiumXI need to use a proper Yosys script I think :P19:35
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ZirconiumXdaveshah: Even just having muxcover alone is a major saving19:43
ZirconiumXEven if 25% of my gates are muxes now19:43
ZirconiumXWas 5,051 ICs, now 4,047 ICs19:44
ZirconiumX...Mostly because the _MUXN_ cells weren't mapped19:45
daveshahYes, you'll need techmap rules (albeit fairly simple ones) to turn them into the relevant 74xx19:46
ZirconiumXPresumably a MUX4 is a 4:1 mux?19:46
tpbTitle: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at
tntWhen implementing a CPU in 74xx, usually you'd also use the OE of the various chips to drive/not-drive shared lines rather than using real muxes, not sure how yosys/abc maps that ?19:48
daveshahI'm pretty sure Yosys can only go in the other direction (from tristates to real muxes)19:49
daveshahusing the `tribuf -logic`19:50
ZirconiumXdaveshah: It's sort of like having an "& !OE" at the end of the output19:53
ZirconiumXtnt: I have fake tristate gates in my library19:55
ZirconiumXEssentially things like 7401s in wired-AND19:56
ZirconiumXApparently ABC really like wired-AND NAND gates19:56
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ZirconiumXThough given that TI apparently don't make 7401s anymore, perhaps I should look for an alternative19:58
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ZirconiumXdaveshah: Presumably replacing these _MUXN_ cells is a good time for _TECHMAP_REPLACE_?20:29
daveshahThat way the name of the _MUXN_ is preserved20:30
ZirconiumXSo, we're now at 4,417 ICs20:38
ZirconiumXSo that's a solid 10% reduction in chips20:38
tntWhat's the target btw ?20:53
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ZirconiumXtnt: As in, target number of chips?21:01
tntno, the target cpu you're trying to implement :)21:04
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ZirconiumXI wanted to design and build a (fairly small) RV32E CPU, but figured Yosys could probably do a better job than me if it knew how21:05
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tntdid you see ?21:07
tpbTitle: Building LMARV-1: a tangible RISC-V processor, part 1 The Half-Baked Maker (at
ZirconiumXAnd a lot of the other ones21:10
ZirconiumXAnd they never got completed21:10
ZirconiumXThough to be fair I don't have particularly high hopes for this21:10
ZirconiumXWe'll see21:10
tntI think an hybrid approach might be the most viable.  Design the "general architecture" manually, thing like registers, source/result bus ... and then use logic for the sub-units to automatically map to availbale logics.21:12
tntjust my 2ct.21:12
tntBecause tbh, 4000 chips seems ... big.21:12
daveshahI think you should be able to reduce the chip count quite a bit if you map RAM to a RAM chip rather than registers21:12
daveshahMight also be worth looking at SERV21:13
tnt is nice but getting yosys to map it is going to be tricky for instance :p21:14
tpbTitle: 74181 - Wikipedia (at
daveshahIf you have some kind of RAM available then SERV should need very little logic compared to picorv32, being bit serial21:14
daveshahCurrently I'd imagine the register file dominates21:14
ZirconiumXYeah, D-flip-flops make up 25% of the benchmark21:15
ZirconiumX50%(!) is MUX4s21:15
tntand how many of those mux4s have their inputs hardwired to 0/1 ?21:16
tnt(i.e. used at LUT2 :p)21:16
ZirconiumXI don't know how to check21:16
daveshahI imagine many of those MUX4s will be mixing DFFs21:16
daveshahYou could try write_verilog and just look at the output21:17
tntAh yeah right, without shared busses / OE would be ... large in mux.21:17
tnt(and without ram)21:17
ZirconiumXSo, there *are* SRAM chips, but they're fairly slow (fastest one I can find is 45ns response time)21:17
daveshahYosys can only map RAM with separate read and write ports at the moment (and a lot of Verilog is written assuming this is available)21:19
daveshahUnfortunately this does limit mapping discrete RAM chips a bit21:19
tntZirconiumX: there are <=10ns sram.21:21
ZirconiumXtnt: Where?21:22
ZirconiumXBecause the main discrete RAM chips I can find are the 62 series (e.g. the 62128 and 62256)21:23
ZirconiumXWhich are 70ns DIP, but less if you use a smaller form factor21:23
tnt(that's just a random one I picked)21:24
ZirconiumXtnt: Sure, but then you have to find chips which have separate read/write ports21:28
tntYou could double pump the SRAM. Or you can use a dural port sram.21:29
ZirconiumXI suppose it also goes against the spirit of building a CPU out of 74 series gates21:35
ZirconiumXIf necessary I'll investigate it though21:35
sorearpeople totally used RAMs in the MSI era21:39
ZirconiumXNot saying they didn't21:39
tntWhat's the widest D ff chip with OE ?21:40
ZirconiumXtnt: I *think* the 74A[H]C16373, which is technically tri-state21:45
ZirconiumXBut there are 16 of them packed into a chip21:45
tntThat's actually a latch, not a ff21:47
ZirconiumXThen it'd have to be the 74x57421:48
ZirconiumXtnt: Actually, how about the 16374?21:50
tntYeah, that would work. You'd need 128 of those for the register bank with two source bus output.21:51
ZirconiumXOkay, so that helps reduce the gate count a bit21:58
ZirconiumXI think I'll use chips from the AC family (which includes the '16374, but not the '150 MUX16)22:00
ZirconiumXdaveshah: Can you get Yosys to turn a MUX16 into a pair of MUX8s and a MUX2?22:00
ZirconiumX(maybe change the muxcover costs?)22:00
tntZirconiumX: what voltage are you targetting btw ? 3v3 ?22:00
ZirconiumXI could consider 3V22:00
daveshahZirconiumX: you can stop muxcover from inferring MUX16s at all22:01
daveshahOtherwise you could have the techmap rule for MUX16s create two MUX8s and a MUX222:01
ZirconiumXtnt: The problem is the distinct non-overlap between logic families22:02
ZirconiumXFor example, the LVC family only has the 157 MUX222:03
ZirconiumXIt is, however, very fast22:04
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