Sunday, 2019-06-16

*** tpb has joined #yosys00:00
*** gnufan_home has quit IRC00:30
*** vid has joined #yosys01:11
*** gsi__ has joined #yosys01:14
*** vidbina has quit IRC01:14
*** gsi_ has quit IRC01:17
*** emeb_mac has quit IRC01:31
*** vidbina has joined #yosys02:09
*** vid has quit IRC02:13
*** flaviusb has quit IRC02:19
*** futarisIRCcloud has joined #yosys02:35
*** emeb_mac has joined #yosys02:46
*** PyroPeter has quit IRC02:57
*** vidbina has quit IRC03:05
*** vidbina has joined #yosys03:09
*** citypw has joined #yosys03:10
*** PyroPeter has joined #yosys03:10
*** vidbina has quit IRC03:14
*** flaviusb has joined #yosys05:16
*** citypw has quit IRC05:25
*** dys has quit IRC05:31
*** dys has joined #yosys05:35
*** rohitksingh has joined #yosys06:00
*** dys has quit IRC06:18
*** dys has joined #yosys06:19
*** citypw has joined #yosys06:50
*** rohitksingh_ has joined #yosys07:08
*** rohitksingh has quit IRC07:08
*** emeb_mac has quit IRC07:17
*** gnufan_home has joined #yosys08:29
*** rohitksingh_ has quit IRC08:51
*** citypw has quit IRC08:53
*** rohitksingh has joined #yosys09:00
*** futarisIRCcloud has quit IRC10:13
*** rohitksingh has quit IRC10:14
*** rohitksingh has joined #yosys10:26
*** futarisIRCcloud has joined #yosys10:54
*** Laksen has joined #yosys11:09
*** rohitksingh has quit IRC11:11
*** AlexDaniel has quit IRC12:13
ZirconiumXIs there any way of redirecting output of a single Yosys command in a script to a file?12:29
ZirconiumXFor example, printing `stat` to a file12:29
daveshahZirconiumX: Yes there is `tee -o`12:31
ZirconiumXThank you!12:32
*** dys has quit IRC12:54
ZipCPUOh wow, thanks daveshah!  I wasn't aware of that.  That will be quite useful to me as I measure component usage!12:55
*** futarisIRCcloud has quit IRC13:03
*** s_frit has quit IRC13:23
*** s_frit has joined #yosys13:23
*** dys has joined #yosys13:32
*** fsasm_ has joined #yosys13:48
*** rohitksingh has joined #yosys13:50
*** rohitksingh has quit IRC14:09
*** rohitksingh has joined #yosys14:21
*** lutsabound has joined #yosys14:21
ZirconiumXIf I wanted to collect stats on which gates are connected to each other, how would I go about that?14:22
daveshahZirconiumX: there is the edgetypes command but  I don't think it tells you how many times each connection type appears14:25
ZirconiumXedgetypes seems confusing to use14:30
ZirconiumXdaveshah: If I get Yosys to hit a log_abort(), should that be reported as a bug?14:37
ZirconiumXEven if I'm doing dumb things?14:38
daveshahI'd say so, unless you're messing with the code or something14:39
ZirconiumXI'm not, so I'll report it14:39
*** AlexDaniel has joined #yosys14:47
*** gsi__ is now known as gsi_14:52
tpbTitle: ERROR: Abort in passes/techmap/ · Issue #1099 · YosysHQ/yosys · GitHub (at
*** cr1901_modern has quit IRC15:04
*** vidbina has joined #yosys15:52
*** emeb has joined #yosys15:55
*** cr1901_modern has joined #yosys15:59
ZirconiumXdaveshah: I want to say thank you for being so friendly and welcoming to me being an idiot.16:20
daveshahHeh, no problem, it's always nice to see interesting uses of Yosys16:21
ZirconiumXI think this is less of a use and more of an abuse16:22
ZirconiumXSomething which is curious to me is that abc doesn't seem to know how to use a mux8 (lut3?)16:23
daveshahYes, that is a known issue iirc16:23
daveshahI don't think anyone knows why16:24
daveshahbtw, ad full adders - probably be better doing what the FPGA flows do; which is `synth -run :fine; techmap -map +/techmap.v -map <custom adder rules.v>; opt`, followed by abc16:25
daveshahrather than trying to extract them after doing synthesis to gates16:25
ZirconiumXYeah, I figured I'd need to do something like that16:25
ZirconiumXI'm wondering what other MSI chips I could add; the 74xx series has synchronous counters, for example,16:26
ZirconiumXBut I'm not sure what kinds of things Verilog usually emits16:26
daveshahI believe Yosys has some support for mapping counters, it's used in the Greenpak4 pass16:27
ZirconiumXI guess the best way of testing the impact of this kind of thing is a large Verilog library that Yosys can synthesize16:28
daveshah has a bit of a range of things16:28
tpbTitle: yosys-bench/verilog/benchmarks_large at master · YosysHQ/yosys-bench · GitHub (at
ZirconiumXdaveshah: Does Yosys not handle `$error`?16:44
*** proteus-guy has quit IRC16:45
daveshahZirconiumX: I think should have added support for that16:45
tpbTitle: elaboration system tasks by cliffordwolf · Pull Request #1077 · YosysHQ/yosys · GitHub (at
ZirconiumX`yosys -V16:46
ZirconiumX` gives Yosys 0.8+531 (git sha1 d4f77d40, clang 6.0.0-1ubuntu2 -fPIC -Os)16:46
ZirconiumXI'm getting a lot of `ERROR: syntax error, unexpected TOK_ELAB_TASK` while trying to parse the ethernet benchmark though16:47
daveshahI think this is a recent regression, Yosys used to ignore them in this context (as is correct for a synthesis tool), but now tokenises them and then fails to ignore them in the parser (because it supports them in `generate` contexts now)16:50
ZirconiumXBug report?16:50
daveshahLooks like should fix it16:50
tpbTitle: Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks) by udif · Pull Request #1086 · YosysHQ/yosys · GitHub (at
ZirconiumXGuess we'll have to wait for Clifford to get round to reviewing it16:51
daveshahI've added a comment to try and speed that up...16:54
*** rohitksingh has quit IRC17:00
*** proteusguy has joined #yosys17:04
*** maikmerten has joined #yosys17:27
*** dys has quit IRC18:17
*** dys has joined #yosys18:32
*** proteusguy has quit IRC18:33
*** proteusguy has joined #yosys18:45
*** vidbina has quit IRC19:15
*** sammylin has joined #yosys19:24
ZirconiumXdaveshah: So, I've been reading the techmap documentation, and the example techmap implementations. If I want to insert a full adder, do I use (* techmap_celltype = "$add" *}19:28
*** Laksen has quit IRC19:37
daveshahZirconiumX: Yes, however, you'll have to make sure you run techmap before alumacc in that case19:41
daveshahalumacc converts arithmetic to more flexible, but more complicated `$macc` amd `$alu` cells (which are probably better suited to mapping things like FPGA carries than discrete chips)19:42
ZirconiumXIs a $macc a multiply-accumulate unit?19:42
*** emeb has quit IRC19:44
daveshahI think so, although I've never worked out it's exact semantics19:44
*** emeb_mac has joined #yosys19:47
ZirconiumXdaveshah: Is it worth having an early and late techmap pass? It seems useful to early-convert $add (74283) and $eq/$ne (7485/7485 with inverter), but late-convert things like counters etc?19:50
daveshahYes, definitely19:50
ZirconiumX"early" and "late" being "before synth" and "after synth"19:50
ZirconiumXCan techmap synthesize a $ne out of a $eq?19:51
ZirconiumX(assuming they are what I think they are)19:51
daveshahYou might need to play around a bit, but I think that should be possible19:51
daveshahBest route might be to take advantage of techmapping being recursive19:52
daveshahSo you write one rule that maps $ne to $eq, and another that maps $eq to logic19:52
daveshah*to chips19:52
ZirconiumXThe 7485 is actually quite versatile; you can use it as a comparator too19:53
ZirconiumXPresumably you'd need to infer that though19:53
daveshahMight be able to map $lt and $gt19:55
daveshahIf you haven't found it already, contains models for all the built in high level cells19:55
tpbTitle: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at
ZirconiumXdaveshah: So to get this to work, I should build a model of the 7485 and then use a _TECHMAP_REPLACE_ for it?20:00
ZirconiumXMy verilog skills feel quite weak at the moment20:00
*** emeb_mac has quit IRC20:01
daveshahNo, with techmapping you don't build a model of the thing you want to map to - instead you describe how to go from a Yosys cell type to the cell type you want to map to20:01
daveshahThis, for example, is an example of techmapping an `$alu` to a mix of soft logic and the hard Xilinx lookahead carry primitives:
tpbTitle: yosys/arith_map.v at master · YosysHQ/yosys · GitHub (at
daveshahor, from a LUT7 to two LUT6s and a MUX2:
tpbTitle: yosys/lut_map.v at master · YosysHQ/yosys · GitHub (at
ZirconiumXSo I'm allowed to pretend that a 74283 exists, even when I don't define it?20:05
ZirconiumXOr whatever20:05
daveshahYou should probably have at least a "black box" - an empty model just specifying what pins are are inputs and what are outputs20:06
ZirconiumXdaveshah: So I just need my transformations to match the API of the equivalent simlib cell?20:17
daveshahYou don't have to handle all cases though, if you set a wire named _TECHMAP_FAIL_ to 1 then Yosys will fall back to its default implementation20:18
daveshahe.g. tells Yosys not to use dedicated logic for adders smaller than four bits (in this case soft logic is more suitable)20:19
tpbTitle: yosys/arith_map.v at master · YosysHQ/yosys · GitHub (at
ZirconiumXSo, for a 74283 (kinda thinking out loud), the maximum per-chip is 4 bit A + 4 bit B + carry in = 4 bit result + carry out20:20
ZirconiumXSo that would expand to recursion of some kind for greater widths, I'd imagine20:21
daveshahThe simplest way would probably be scaling both inputs to a common size, then using a generate for loop to instantiate the adders20:23
ZirconiumXHow would I chain carries between generate for iterations?20:34
daveshahYou can a wire for the intermediate signals20:35
daveshahSort of like how C and CO are used here:
tpbTitle: yosys/arith_map.v at master · YosysHQ/yosys · GitHub (at
*** maikmerten has quit IRC20:49
ZirconiumXVerilator is being helpful as ever >.>20:49
tpbTitle: [SystemVerilog] module \74283 (A, B, CI, S, CO); input [3:0] A; input [3:0] B; input CI; o - (at
ZirconiumXVerilator complains here20:51
ZirconiumXAnd using techmap on it infinite loops20:51
ZirconiumXThough I realise there's obvious bugs20:51
ZirconiumXI'm not sure how to pad the input and output buffers though20:52
ZirconiumXAh, a buffer20:53
ZirconiumXI think20:53
*** fsasm_ has quit IRC20:54
daveshahZirconiumX: you need to add `(* blackbox *)` to the 74283 model20:55
daveshahOtherwise Yosys looks inside it, which you don't want in this context (because it will recursively techmap the add inside it)20:56
ZirconiumXThat makes sense20:56
daveshahNormally, the idiom is to put all the sim models in a separate Verilog file to the techmap rules, and read that file in Yosys with read_verilog -lib20:57
daveshahThat implies blackbox on all the sim models20:57
daveshahI'm also not sure if _TECHMAP_REPLACE_ will work here20:58
daveshahIt's intended for 1:1 techmapping, might cause problems when you map to more than one cell20:58
daveshahI'd name the instance something else meaningful like adder_i20:59
*** gnufan_home has quit IRC21:01
*** gnufan_home has joined #yosys21:03
tpbTitle: (* techmap_celltype = "$add" *) module _80_74283_add (A, B, Y); parameter A_ - (at
ZirconiumXdaveshah: How does this look?21:04
ZirconiumX(I just noticed CARRY; I'll remove it)21:04
ZirconiumXThis should have a carry-in, but I don't know what to set it to21:05
ZirconiumXA_SIGNED ^ B_SIGNED?21:05
daveshahYes, that makes sense21:06
ZirconiumXThough, a value being signed or not does not imply whether it's positive or negative21:06
daveshahActually, I think just leave CIN at zero21:07
daveshahAlso, might need a temporary signal for Y, otherwise it will go out of bounds21:07
ZirconiumXI'm mostly just translating from the iCE40 arith_map.v21:08
daveshaheg. have a YY signal of width WIDTH, then do `assign Y = YY[Y_WIDTH-1:0];`21:08
daveshahLine 32 might go out of the bounds of Y when width isn't a multiple of four otherwise21:09
ZirconiumXShould A_conv and B_conv be WIDTH instead of Y_WIDTH too?21:10
daveshahNo, that doesn't matter, the upper bits of A and B don't matter21:10
*** gnufan_home has quit IRC21:11
tpbTitle: [SystemVerilog] (* techmap_celltype = "$add" *) module _80_74283_add (A, B, Y); parameter A_ - (at
ZirconiumXYosys is complaining about line 4221:17
daveshahwire [WIDTH-1:0] YY = Y_buf; should be the other way round21:18
daveshahY_buf = YY;21:18
*** sammylin has quit IRC21:19
ZirconiumXdaveshah: But then YY isn't defined, right?21:23
daveshahAh yes, you'll also need to change the definition of Y_buf to define YY instead21:23
ZirconiumX <-- I fixed the assign Y = Y_buf line instead21:25
tpbTitle: [SystemVerilog] (* techmap_celltype = "$add" *) module _80_74283_add (A, B, Y); parameter A_ - (at
ZirconiumXYosys no longer complains at least21:25
daveshahYou can get rid of Y_buf altogether, as you're now just using YY and Y, which is fine21:29
daveshahRemove Y_buf and just do wire [WIDTH-1:0] YY;21:30
ZirconiumXWhat about A_buf and B_buf?21:31
ZirconiumXSome stats, if you want a laugh21:32
daveshahIf you drive AA and BB from the `$pos` looks like they can be removed too21:32
ZirconiumXBefore, to go through my benchmark of various things, you'd need 7,340 ICs21:32
ZirconiumXNow that Yosys recognises the 74283, you now need only 4,23721:32
daveshahVery nice!21:32
daveshahWhat is your synthesis script?21:33
ZirconiumXread_verilog $<; hierarchy -auto-top; read_verilog -lib ../74_models.v; techmap -map ../74283.v; s    ynth -run :fine; techmap -map +/techmap.v; opt; dfflibmap -liberty ../74series.lib; abc -liberty ../74series.lib; te    e -o [email protected] stat21:33
ZirconiumXPlus or minus awkward formatting (thanks Vim)21:33
daveshahTry running `proc; opt; wreduce; opt` before mapping the 7428321:34
daveshahIt might reduce the width and number of adders slightly21:34
ZirconiumXI appear to be leaking some $mem cells21:36
ZirconiumXYour pre-map optimisation seems to bring the number of ICs way back up to 6,23121:38
ZirconiumX(still less than before, at least)21:38
ZirconiumXYeah, your optimisation leaks $mem cells21:39
*** vidbina has joined #yosys21:39
daveshahOh, that's odd21:39
daveshahWhat if you add `flatten` between `proc` and `opt`21:41
ZirconiumXStill leaking $mem cells, but now we're down to 3,010 ICs21:42
*** futarisIRCcloud has joined #yosys21:43
ZirconiumX(PicoRV32 is now 1,018 ICs; it was 2,003 yesterday)21:43
daveshahTry running `opt - full; memory_map; opt -full` after `synth -run :fine`21:44
daveshahRight now nothing in that script is actually mapping memory to logic21:44
daveshah*`opt -full`, no space between - and full in either case21:45
ZirconiumXNo more leaking $mem cells21:45
ZirconiumXBut one of the example benchmarks doesn't synthesize21:46
ZirconiumXLooks like I messed up the adder?21:46
ZirconiumXERROR: Output port smartbextdep.$techmap\smartbextdep_direct_inst.decoder.pps_core.$add$../benchmarks/smartbextdep.v:245$1677.slice[0].adder_i.CO (\74283_1x1ADD4) is connected to constants: 1'x21:48
daveshahZirconiumX: Make C `WIDTH:0` rather than `Y_WIDTH:0`21:49
daveshahin the techmap rule21:49
ZirconiumXYep, that fixes it, thank you once again21:50
ZirconiumX5,051 ICs for the benchmark here21:51
ZirconiumXBut all of the benches build at least21:51
ZirconiumXAnd we're still doing better than before21:51
ZirconiumXHave I thanked you enough, daveshah? I'm not sure I have.21:59
*** vidbina has quit IRC22:09
*** gnufan_home has joined #yosys22:26
*** s_frit has quit IRC23:38
*** s_frit has joined #yosys23:39

Generated by 2.13.1 by Marius Gedminas - find it at!