Saturday, 2019-06-15

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promachWould it be nicer to use  negative edge triggered 'reset' compared to its positive edge triggered counterparts ?02:32
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ZirconiumXHere's a probably quite cursed idea.18:04
ZirconiumXYosys supports reading Verilog, optimising it, and writing it as BLIF18:04
ZirconiumXIf you then use misII, which is a UCB tool from the 90's, you can read BLIF and turn it into 74-series logic18:05
ZirconiumX"But why?"18:05
ZirconiumXGood question18:06
tntWhy cursed ? I mean, if you need some logic done in 7400 that could be a totally valid way to find a solution possibly better than what you can come up with manually.18:08
ZirconiumXTrue, but it's a very hacky way of doing it18:09
tntMaybe yosys has a 74 series mapping library natively ?18:09
ZirconiumXThat's a question; how would you write one?18:14
tntno clue18:15
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ZipCPUZirconiumX: Check out the ABC pass.  synch + abc can be used to map a design to a variety of simpler logic circuits, such as you might use with 74-series logic.  It's not specific to it, but I think it should work19:11
ZipCPU"But why?"  My son came home from college a semester ago with a requirement to design a particular 7-seg display circuit from straight logic gates.  It's a whole lot easier to design and test in Verilog.  Why no use Verilog, formally verify it, and then map it to gates using Yosys?19:12
daveshahABC can natively map simple gates, for fancier gates you could write a Liberty file (like to map to19:15
tpbTitle: yosys/cmos_cells.lib at master · YosysHQ/yosys · GitHub (at
ZirconiumXI want to experiment with designing and building a CPU out of 74-series logic19:15
daveshahBut neither of these approaches support multiple-output gates, so you'd still be mapping gates rather than chips19:15
daveshahi.e. you won't get a minimum-chip solution19:15
ZirconiumXAnd, yeah, formal verification would be a bonus19:15
ZirconiumXdaveshah: Maybe you could approximate it by tuning the area settings19:16
daveshahYes, you could19:16
ZirconiumXFor example you can fit two 4-input muxes in a 74153, but only one 8-input mux in a 7415119:17
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ZirconiumXdaveshah: So do I need to make an equivalent cell for AND/ANDNOT/whatever, or do I make my own cells and let ABC figure it out?19:32
daveshahZirconiumX: I believe ABC needs three cells minimum: buffer, NOT and a logic gate (don't think the kind of gate matters much)19:34
daveshahOtherwise it won't be happy19:34
ZirconiumXDo they need to explicitly be named BUF/NOT/etc?19:38
daveshahNo, only the function matters19:39
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ZirconiumXPicoRV32 apparently synthesizes to 398 7400 gates (so 99 ICs), and 93 7404 gates (so 16 ICs)19:49
daveshahThat seems very low19:50
daveshahMaybe that isn't mapping the memory for some reason19:50
daveshah*register file19:50
_vinceany comments on the chip stats? what's the most common chip in that circuit?19:50
ZirconiumXSince it only currently understands the 7400, 7404 and 74367, don't expect miracles19:51
daveshahThe register file should need at least 1024 bits of state, so something must be going wrong19:51
_vincehand optimizing 74s is fun ZipCPU probably why they are making him do it19:51
_vincei had those kinds of exercises in high school electronics19:52
_vincedefinately a crude 7segment clock was a topic but with a lot of help - we didnt have to design everything19:52
_vinceor was it that there was a 7s driver19:52
_vincewith BCD input or something19:52
ZirconiumXYeah, abc does not like multi-output gates19:55
ZirconiumXI got an assertion failure in Yosys19:55
ZirconiumX(why do I keep breaking this poor, poor program?)19:55
ZirconiumXdaveshah: `hierarchy` appears to be pruning picorv32_regs?19:57
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daveshahI think picorv32_regs is an example of an external register file, picorv32 will use a built in one by default (set by a macro)19:59
daveshahSo I doubt that is the problem19:59
daveshahYou probably want `hierarchy -top picorv32; flatten`19:59
ZirconiumXOkay, that seems more reasonable20:00
ZirconiumX3,722 7400 ICs, 579 7404 ICs, 6 74367 ICs20:02
daveshahI think you'll also need to map DFFs seperately - see `dfflibmap`, `abc` in this context will only map combinational logic20:03
daveshahThat sounds about right20:03
ZirconiumXSo presumably for DFF I need to include D flip-flops?20:05
daveshahYes, and `dfflibmap`  will map them seperately20:05
ZirconiumXDoes it expect each flop to have its own clock?20:06
daveshahYes - even though this isn't actually true for FPGA flows, usually this would be resolved in placement down the chain20:06
ZirconiumXGonna be fun finding an equivalent chip then20:06
daveshahHowever, if there is only one clock in the design (as is the case with picorv32) then all flops will use that clock20:07
daveshahYosys won't create clocks out of nowhere20:07
ZirconiumXThere's the '574, but that only have one clock for 8 bits20:07
daveshahThat will be fine20:07
daveshahI struggle to think of a design that has one clock domain for fewer than 8 bits...20:08
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ZirconiumXSo after adding a '574, dfflibmap is still complaining about unmapped cells20:16
ZirconiumXDFFSR, which I think means a set-reset flip-flop?20:17
ZirconiumXAnd also things like $_DFF_NN0_20:17
ZirconiumXdaveshah: ^20:17
daveshahIs this with picorv32? These would be DFFs with async set/resets20:18
daveshahWhich I didn't think picorv32 had20:18
ZirconiumXYes, it is20:18
tpbTitle: 5. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty - (at
daveshahAh it's only saying it didn't find these cell types in the library20:19
daveshahBut in this case it shouldn't need to map any of them20:19
daveshahYou can check by running `stat` after `dfflibmap`20:20
daveshahThis will show if there are any of these DFF types left unmapped20:20
tpbTitle: 7. Printing statistics. === picorv32 === Number of wires: - (at
daveshahLooks good, looks like it mapped all the DFFs20:22
ZirconiumXThere is something quite amusing about this; using Yosys to design 1970's era logic20:25
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tpbTitle: 7. Printing statistics. === picorv32 === Number of wires: - (at
ZirconiumX7,583 cells21:01
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ZirconiumXI can synthesize VecRiscV too21:11
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ZirconiumXZipCPU: So it seems like formally verifying a CPU made out of 7400 logic might actually be possible21:19
ZirconiumXAlthough the "single output pin" problem is fairly crippling21:19
ZirconiumXAlso dfflibmap does not like the idea of output-enable bits21:21
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