Friday, 2019-05-24

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adamgreigdaveshah: i think commit has broken all my multi-clock bram inference on ice40 :p18:02
tpbTitle: memory_bram: Fix multiclock make_transp · YosysHQ/[email protected] · GitHub (at
daveshahadamgreig: it was always broken :p18:02
daveshahjust not so visibly...18:02
adamgreigwell before it worked and now it tries to use 65000 LCs instead of a few brams18:02
adamgreigso i guess i didn't notice the broken before but now it really is broken :P18:02
daveshahThe iCE40 doesn't have a hardware transparent (write-through) BRAM mode18:03
adamgreigaha, that might be a good clue18:03
daveshahIt is possible to fake this for a single clock domain, but afaik there is no guaranteed safe solution across clock domains to fake it18:03
daveshahBefore Yosys tried, but this led to odd sim-synth mismatches18:04
adamgreigI don't really care about write-through but I'm using nmigen and it might well be asking for that by default18:04
daveshahoMigen/LiteX definitely supports both18:04
daveshahI've seen both in its Verilog output18:05
daveshahnot sure about nMigen, maybe it is an option?18:05
adamgreigit is an option on the read port18:05
adamgreigI'll see if that fixes things18:05
adamgreigyikes. it's certainly done something.18:10
adamgreignow I have hundreds fewer LCs and also no RAMs18:10
tntadamgreig: what does the verilog look like18:16
adamgreignmigen generates RTLIL rather than verilog though I do have a minimal test case18:16
adamgreighowever I think I've solved it now18:16
adamgreigI have to set transparent=True on the read port to allow yosys to infer it for ice4018:17
adamgreigbut then nmigen changes the read port enable from constant 1 to some undriven signal which resets to 0, so the read port was always disabled, which is why most of my design subsequently vanished18:17
adamgreigif I set transparent=False and assert rport.enable to 1 it all seems to work18:17
adamgreigso... user error I guess! albeit some slightly confusing api design18:18
adamgreigthanks daveshah!18:18
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