Wednesday, 2019-05-15

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plaesany idea whether there are boards that support muxing two hdmi streams into single one that also support open tools?08:15
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tntplaes: don't think so. Only working open tools are ice40 and ecp5 (I mean those with enough maturity to go from .v to bitstream for that kind of non-toy project).  ice40 is way too small for that. And I have not seen any ecp5 board with 2 hmdi in and 1 hdmi out.08:19
plaesok, quick googling gave me Numato Opsis (with Spartan-6) and NeTV2 (with Artix-7 but not yet readily available)08:28
tntyup those would have been my recommendations if you didn't require open tools.08:30
tntbut the netv2 is available afaik.08:30
tntcrowdsupply shows it "in stock".08:31
plaeshmm.. cool08:33
tntI'd go with the netv2.08:35
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plaesooh.. Project X-Ray08:43
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PostmanmodsHi everyone! I have a question about yosys synthesis process vs the icecube process... Have been banging my head against this for a while now and can't seem to find a solid answer.16:47
PostmanmodsI have a verilog program that synthesizes in yosys in about 20 seconds and works fine on my ice40hx1k but takes ~3 hours to synthesize and uses 10,000% of my allocated LUTs on icecube2! What am I missing?16:48
tntPostmanmods: you're probably relying on it to infer a RAM16:51
tntand inferring stuff ... is ... unreliable depending on what the tool support.16:51
PostmanmodsBear with me as I am dipping me feet into FPGA for the first time with this project I have undertaken.16:52
tntpost your verilog somewhere16:52
Postmanmodskk just a sec... It has a lot of nested if statements which I hear is a big no no in verilog.16:53
ZipCPUCould also be the result of a multiply within the code as well.16:56
tpbTitle: `default_nettype none disable implicit definitions by Verilog //apio build --si - (at
PostmanmodsIt's... Rough... I know. First verilog project that I cobbled together.16:57
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ZipCPUOk, lines 49 and 54 or a problem ...16:57
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ZipCPUCheck out the block RAM rules in
PostmanmodsWill do. Is it an issue with my code or the way I configured the synthesis?17:00
tntZipCPU: why ?17:00
ZipCPUIn particular, your design breaks rule #3--and so yosys cannot manage to turn it into a RAM17:00
ZipCPUtnt: His design cannot map to the iCE40 hardware as written17:00
tntZipCPU: yosys works fine, icecuble doens't AFAIU17:00
ZipCPUHeheh ... yosys has some fun little clean up pieces of logic that not all of the big synthesizers support17:01
PostmanmodsYeah, that's what I am trying to reconcile. The code compiles and works perfectly from spi flash.17:01
PostmanmodsGrrrr, thats what I figured!17:02
ZipCPUYou could make the #46-60 block work if you calculated the memory address combinatorially17:02
tntZipCPU: I don't see why it couldn't map. A mux on the write address input to switch between 0 and waddr would work fine.17:02
ZipCPUYes, exactly--yosys does that, but many vendor synthesis tools will not17:02
ZipCPUMany of the vendor synthesis tools are *really* strict when about what logic will infer block rams and which logic will not17:03
tntSorry I misunderstood, I thought you said there was no way to produce logic what would implement that behavior.17:03
PostmanmodsSo I have a second question, this one about NVCM.17:03
ZipCPUtnt: I did say that, didn't I?  But if it works in yosys and not the vendor tool, then that can't be it.17:04
* ZipCPU google's NVCM, gets: "Noe Valley Chamber Music"17:04
tntWell " His design cannot map to the iCE40 hardware as written" ... I understand this as there is not theoritical way you could map that verilog to an ice40 design that implements it.17:04
* ZipCPU tries duck duck go, gets "New Vision Christian Ministries"17:04
Postmanmods2x LOL17:05
tntNon Volatile Configuration Memory17:05
ZipCPUtnt: Yes.  That's usually what's going wrong, but ... not in this case.  (i.e. I was wrong.  Oops)17:05
PostmanmodsNon Volatile Configurable Memory, for one time flashing17:05
* ZipCPU needs to step away ...17:05
tntwhat about it ?17:06
PostmanmodsIs it possible to generate a nvcm bitmap from yosys for an ice40?17:06
PostmanmodsOr is that a vendor app only thing?17:07
tntis the nvcm bitmap different from the normal bitmap ?17:07
PostmanmodsI think? One sec, lemme double check.17:08
PostmanmodsOh jeeze, they might be the same. Lemme post a .nvcm file for reference.17:09
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PostmanmodsReal quick, thank you sincerely. Learning FPGA is one HELL of a steep learning curve.17:10
tpbTitle: #DF 4-15-2019 #DC 512a #SR 2017.08.27940 #DN iCE40HX8K #PT CT256 #HF 01 06 - (at
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ZipCPUtnt: The reason for my earlier answer was that I've been burned several times over by the fact that the iCE40 hardware requires that the output of any memory read be registered.  I was a bit hasty, before looking at the code, to conclude that was the problem since it's a common ice40 problem that you have when porting "working" designs to the iCE4017:28
ZipCPUPostmanmods: I'm not sure I know the answer to that one.  I've never successfully loaded an iCE40 from flash, more from a lack of trying than anything else17:29
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tntZipCPU: heh no worries. I actually misread you answer, I read "I didn't say that did I" instead of "I did say that, didn't I" :p  so I guess we both read too quickly.17:34
ZipCPUSometimes I think it's a trait of a "good" engineer.  :D17:35
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tntThe 'reset to 0' of the read register is also a common reason bram mapping fails.17:36
tntIn general I put all my inferred logic in a separate module with just that in it to try and make it as easy as possible for the tool to notice.17:37
tntBut icecube is really dumb ... I mean even a non-power of 2 memory depth prvents mapping.17:37
emeb I've noticed that too.17:37
PostmanmodsOk so its most likely a case of lattice's sorftware being picky.17:40
PostmanmodsSo that means a code clean up if I want a well optimized bitstream?17:40
emebAFAIK the NVCM on iCE40 is programmed with the same bitstream format you'd load into the RAM directly, or into external SPI flash. But iceprog doesn't seem to support talking to the NVCM and I've heard that there's some sort of special unlock sequence needed to access it.17:41
emebAll that, plus the fact that it's OTP and I've avoided it.17:41
tntSomeone just needs to sniff and document it ...17:42
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PostmanmodsI actually jimmy rigged an ice40 with an rs2232 to interface with the spi. Diamond programmer actually sees it and writes the CRAM!17:42
PostmanmodsBetter than paying $200 for Lattice's overpriced POS...17:43
tntyou mean ft2232 ?17:43
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PostmanmodsOh thank you,yes.17:43
PostmanmodsNot serial lol17:43
PostmanmodsI'll let you guys know what I find in my NVCM adventures. It would be really helpful for to use for some applications.17:47
emebIt would be great for a default bootloader17:48
emeband of course for low-cost / high volume stuff that's not expected to change. But who in this space ever does that? :)17:48
tntemeb: unfortunately if NVCM is enable WARMBOOT doesn't work :/17:50
emebtnt: ouch! missed that detail.17:51
tntyeah :/17:52
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emebSo if the NVCM is enabled you can't use external SPI flash - only option is slave configuration.17:58
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emebInteresting reading about Cold Boot mode - wondering how the device differentiates between an external  SPI flash that has the "Cold/Warm Boot applet" and one that's just raw bitstream.18:08
emebmust be some reserved bits in the start of the bitstream...18:08
PostmanmodsNo no, I was reading about a dual boot feature... Can't back that up with a source rn but I think it may be possible.18:15
PostmanmodsIt is also an option in the Diamond programmer utility so there's that too.18:15
tntSB_WARMBOOT and the multiboot header.18:15
PostmanmodsAh, right18:16
tntyou can specify 5 images in a header at the beginning of flash. First one is the one loaded by default. Then via the warmboot primitive the design inside the fpga can trigger a reload of any of the 4 other images.18:16
PostmanmodsNo documentation on that in my findings unfortunetly /:18:16
PostmanmodsDang... That would be so nice for prototyping.18:17
PostmanmodsHave a polished design in the nvcm and rough code on the flash18:17
tntexample :
tpbTitle: ice40-playground/ at usb-test · smunaut/ice40-playground · GitHub (at
PostmanmodsOh nice18:18
Postmanmodsso these are python scripts for this dev board?18:19
PostmanmodsErr, any dev board rather.18:19
tntwell (1) it's mostly verilog, there are a few python helpers   (2) with changes to the pcf you can make it work on many ice40 boards.18:19
tntthis whole repo is just where I put my ice40 stuff so I can easily share the 'reusable' cores between projects.18:20
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PostmanmodsCool! Thanks for the resource, I will poke at it when I get a chance. Should be fun.18:25
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PostmanmodsZipCPU IT WORKED!23:33
tpbTitle: Imgur: The magic of the Internet (at
PostmanmodsDid I tag him correctly? Still used to discord.23:34
PostmanmodsBut you were correct, it was a blocking issue. Thank you so much for the advice, I spent an embarrassing amount of time on that...23:34
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ZipCPUWha .. wha .. what happened!  Did it work?23:51
ZipCPUPostmanmods: Did I miss something?23:52
PostmanmodsOh, the link you sent me23:55
ZipCPUDid that help?23:55
PostmanmodsIt turned out my issue was exactly what you said! I rewrote the blocking for the memory I/O and BOOM. Synthesized in icecube2 in 60 seconds flat with 30% LUT usage! :D23:56
PostmanmodsThank you so much, I could not understand why it was having such issue. You made my week man.23:57
PostmanmodsSo you have a website with other resources like that?23:57
ZipCPUThere's a lot of really useful information in those tutorial slides.  You can find all of them from
tpbTitle: Verilog, Formal Verification and Verilator Beginner's Tutorial (at
ZipCPUI've tested many of the designs on iCE40s too--although I have left some errors behind in most cases for you to find ;)23:58
PostmanmodsI love the tuts, concise and to the point with examples.23:58
ZipCPUThank you23:58
Postmanmodshaha wonderful, debugging the tutorials code. Great way to learn!23:58
ZipCPUWell, isn't it?23:59
ZipCPUThe last statistic I learned suggested you'd spend 30% writing your code, and 70% making sure it works23:59
ZipCPUIf you are going to spend that much time getting it to work, shouldn't instruction be focused on that part of the design process?23:59
ZipCPU... or at least that was my thinking when putting the slides together23:59
PostmanmodsSince I started learning about FPGA's I haven't really found any solid resources. Even the manufacturers info is meh at best.23:59

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