Tuesday, 2019-05-14

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dormandois it possible to get nextpnr to visualize/outline wires specific to a module?04:17
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tntdormando: not that I know.04:54
tntyou can select them one by one ...04:54
dormandoheh. I did that for a few minutes. it's the one thing I miss from the ISE atrocity04:55
tntMaybe a small python script could help.04:55
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bluesceadahey everyone, i want to NOT initialize BRAM in my ice40, to analyze the start up state of RAM, this is possible in lattice icecube2, but how would it be possible with yosys/nextpnr ?12:57
bluesceadai am already using the bare SB_RAM40_4K, but that alone doesn't help it12:57
bluesceadai tried withou specifying parameters, and I tried with giving all INIT parameters don't care's like: .INIT_0(256'hxxxx....xx) to .INIT_F(256'hxxx..xx)12:59
bluesceadain icecube2 we need to check a box in the tool to not initialize memories, while somewhere else they document to use the SB_RAM40_4K as a non-initialized memory ... but it soemhow is always reset to all-0's13:01
bluesceada(if we do not check the box, that is, otherwise it contains all seemingly random data)13:01
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tntbluesceada: not sure it's supported13:15
bluesceadaok let's wait a bit if someone else shows up that might know13:16
tntI'm looking at the icepack sources and I don't see anything that would disable it.13:20
bluesceadaah thanks for looking into it, you mean disabling the initialization?13:28
bluesceadaseems yosys also goes with 'xxxx', so it must happen after yosys13:29
bluesceadaso, probably the x will be replaced with 0 in some later step?13:29
tntyeah, that's the very last step when converting the .asc into the .bin file ...13:29
bluesceadaor rather, if there is no initialization, the packer will make it initialize to 013:29
tntso even if supported this wouldn't be in verilog, it would be an option during the icepack step.13:30
bluesceadaok that would also be fine of course13:30
tntbecause as discussed recently you can't do that "per bram", it's per quadrant.13:30
bluesceadaok yes I think that is also how it's shown in icecube213:31
tntyou can try to comment out https://github.com/cliffordwolf/icestorm/blob/master/icepack/icepack.cc#L53813:32
tpbTitle: icestorm/icepack.cc at master · cliffordwolf/icestorm · GitHub (at github.com)13:32
bluesceadayou think that complete if {..} ?13:34
tntI'd try that yes13:43
tnttrying to make a PUF btw ?13:47
bluesceadatnt, yes, for the students in my lab13:48
bluesceadathat used icecube2 before13:49
bluesceadabtw it seems to work, partially13:50
bluesceadaseems every second byte is still 00, but that might be another problem13:51
bluesceadafrom comparing the bitstream filesizes, it is now roughly on par with the icecube2-non-initialized one, but not exactly the same size14:01
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bluesceadaok got it, will try to make it a pull request for icepack soon...15:07
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bluesceadatnt, it was actually right what you said and I had another issue with word/byte addresses, however I also found that it is sufficient to exclude the last part of that if-condition in which BRAM is initialized15:07
tntbluesceada: yeah, very possible you can comment less, but the rest of the commands written in that block wouldn't have any effect if you don't write any data, so they're useless.15:10
tntbut you could make the option allow to specify which bank # you want to include or not, maybe as a bitmask15:10
bluesceadaok i thought these might have to do with the mode of addressing, but yeah in the end it was wrong verilog15:11
bluesceadai dont have much time for this so I would just add a simple option ...15:12
bluesceadanext thing we need later in the semester will be placement constraints, but i see this has been added to nextpnr :-)15:13
bluesceadaso this lab will be completely on open source software :-)15:14
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tntsyntax is different than icecube for placement. (tbh I'm not even sure what the syntax was for icecube)15:15
bluesceadai think it is better, can work inline verilog code15:15
bluesceadamore similar to how xilinx supports I think15:15
bluesceadabut have to still take a closer look..15:15
tntDo you have an example howit was for icecube ?15:15
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bluesceadait needs to be inside the constraints file, not easy to handwrite imo, generated from the icecube gui15:19
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bluesceadaif you want a full example, i can somehow make it accessible to you15:21
tntnah it's fine, I was just curious15:22
bluesceadaprobably not too bad to support both ways15:22
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bluesceadafor xilinx i was using a LOC constraint in a constraint file to place a full block. Then, within the block, relative location constraints (RLOC) as vhdl attributes (also works in verilog)15:24
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mithroAnyone know the best way to write a yosys pass that would propagate parameters following signal input / output cones?21:23
mithrodaveshah: would this be something you could do with the new python API?21:28
mithroAnyone used the new Python API in Yosys?21:29
daveshahmithro: I haven't used the Python API yet, but this is the sort of thing it is designed for21:30
mithrodaveshah: Is there any examples I might be able to crib from?21:31
daveshahmithro: https://github.com/YosysHQ/yosys/tree/master/examples/python-api21:31
tpbTitle: yosys/examples/python-api at master · YosysHQ/yosys · GitHub (at github.com)21:31
mithrodaveshah: Thanks!21:32
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