Monday, 2019-05-06

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promachZipCPU: not sure why yosys sby formal tool gave me that initial unknown thing. I will use iverilog and vivado simulator and solves most of the problems first02:51
ZipCPUYeah, me neither--since the formal tools have never given me 'x's before02:52
ZipCPUAre you sure you had -formal specified in your sby file?02:52
* ZipCPU is just making wild guesses at this point, having never seen this before02:52
tpbTitle: Spidergon Networks On Chip ยท GitHub (at
ZipCPUTry using read_verilog -formal, and see if that makes any different from read_verilog -formal -sv03:02
promachyou mean without  -sv    ?03:03
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ZipCPUIt shouldn't make a difference since you don't have the sv license anyway03:06
ZipCPUAlthough, you should know that the "read" command supercedes "read_verilog", but that discussion can wait for another day03:07
promachI guess the issue lies somewhere else other than the sby file ;|03:07
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ymherklotzHi, I would like to load a verilog design in yosys and append a string like "_1" to all the modules21:29
ymherklotzusing 'rename mod1 mod1_1' works, however, I saw that yosys has a -enumerate option21:30
ymherklotzI can't seem to get it to work though, I have tried rename -enumerate A:* and selecting all the modules before calling rename -enumerate21:30
daveshahAs far as I know, -enumerate is intended to give things with dollar-prefixed internal names shorter names21:32
daveshahIt's not for renaming user modules21:32
ymherklotzAh ok, so it does not work on modules?21:32
daveshahrename does, but -enumerate doesn't - it is for nets and cells with dollar prefixes (typically ones generated by Yosys)21:33
ymherklotzAh ok, is there another way I could batch rename modules? Or should I just stick to doing it individually?21:33
ymherklotzI'm asking because I want to compare two designs that have the same module names in one top level module21:35
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daveshahI think you have to do it individually21:36
ymherklotzGreat thanks!21:37
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