Saturday, 2019-05-04

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promach_For and , why am I having  "xxxxx" unknown signal ?05:59
tpbTitle: Spidergon Networks On Chip ยท GitHub (at
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ZipCPUpromach_t: Because you never initialized the signal10:24
promach_ZipCPU: huh ?10:26
promach_see the other flit_data_output signals10:26
promach_only flit_data_output<3> has unknown signal10:27
ZipCPUWheres the initial statement giving it an initial value?10:28
ZipCPUI looked and didn't see it10:28
promach_ZipCPU: I have added   initial flit_data_output[port_num] = 0;   , but same "xxxxx" unknown signals10:32
ZipCPUThat's the problem.  Keep working with it, and you should have it working10:35
promach_ok, but I am not sure why the initial statement is not helping10:45
ZipCPUI'd have to see more details to know10:50
* promach_ will leave this piece of verilog code until monday morning11:04
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promach_is there a way to make formal tool start BMC timestep 0 with a negedge instead of a posedge ?15:16
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promach_ZipCPU: I think I found why... but it requires the formal tool to start with a negedge15:24
promach_line 377 is for the reset15:26
promach_and I have   initial assume(reset);15:26
promach_but then,  initial flit_data_output[port_num] = 0;  should have eliminated the "xxxxx" unknown signal .... :|15:35
promach_I think I will just leave this until Monday ....15:36
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