Wednesday, 2019-05-01

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mithroZipCPU: You any good at understanding `select` commands?19:03
ZipCPUHow so?19:03
mithroActually, firstly - does Yosys have a `-Werror` type flag?19:04
* ZipCPU looks up select commands19:04
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ZipCPUNot that I know of.  I use verilator _Wall to as a lint checker19:05
ZipCPUSorry, verilator -Wall -cc19:05
mithroI really want to turn this warning into an error -> Warning: wire '\o1' is assigned in a block at dff_two_clocks.sim.v:11.19:06
mithroZipCPU: Because that actually seems to be the issue with my select commands...19:06
ZipCPUAre you familiar with that warning?19:07
ZipCPUThat one was put into Yosys at my request19:07
ZipCPUIt basically means that o1 was defined as a "wire" (not a "reg") and then assigned within an always @(*) block19:07
ZipCPUVerific catches these things and returns them as errors, so I thought Yosys should as well19:08
ZipCPUInternally, however, yosys doesn't really treat wires and reg's all that differently19:08
ZipCPUBut ... at this point I'm probably not answering your question anymore ;)19:08
emebZipCPU: for most of my career I've been a Verilog coder. Then, about 8yrs ago I had to switch over to VHDL. This has made me appreciate languages that are much more strict.19:09
daveshahmithro: You can use -e regex to make a warning matching a regex into an error19:10
emebHaving to run my Verilog thru a few different tools which are persnickety about different things is annoying. I started using Verilator for linting a while back and this makes me happier.19:11
mithrodaveshah: Oh? Where do I pass that?19:11
daveshahTo the Yosys main command line19:11
daveshahThere are a few other similar options that may be of interest too, see yosys -h19:11
ZipCPUemeb: o/  If there's one thing that annoys me, its verilog code that works fine with one parser from one vendor's tool, but not with another19:13
emebZipCPU: Just so.19:15
mithroyosys -e "wire '[^']*' is assigned in a block"19:21
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* ZipCPU scratches his head confused19:24
daveshahThat looks correct to me19:24
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sielickiOne of my classes required us to write very backwards verilog at the beginning of the class, and now our class project is nearly complete and I'd like to remove some of the cruft that we had to use.22:38
tpbTitle: assigns-sielicki/xnor5_1.v at synthesis · cs-ece-552/assigns-sielicki · GitHub (at
sielickiI want to propagate removal of just a set of these backwards / useless modules, across all modules. Not for any sort of synthesis reason but just for the sake of cleaning things up. I'm probably spending more time playing with yosys than it would take to just do it by hand, but I'm curious if anyone can help me figure out how to get my script in working order.22:40
sielickiHere's what I currently have:22:40
sielickiThis is ultimately not what I want. Been pouring through the docs here for a bit.22:41

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