Monday, 2019-04-15

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promachFor , why am I having this error "[spidergon_proof] base: spidergon_router.v:343: Warning: Range [1:-1] select out of bounds on signal `\data_input': Setting 1 LSB bits to undef." ?09:25
tpbTitle: Spidergon Networks On Chip ยท GitHub (at
promachIf I change (FLIT_DATA_WIDTH-1) to 7 , I have different error09:31
promachit seems like the verilog code parser treats (FLIT_DATA_WIDTH-1) and 7 differently.  Note that FLIT_DATA_WIDTH has a value of 809:31
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promachZipCPU: have you experienced similar issue previously ?10:37
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ZipCPUpromach: Yes, I have had similar issues, but the were all traced in the end to issues within my own code11:21
ZipCPUIn your case, lines 7-9 are missing the keyword "parameter" as are 11-1311:22
promachZipCPU: no11:37
promachI have added parameter as you advised, but same error11:38
promachI think I know why now11:43
promachI have one other bug11:43
promachI just got past this particular error11:47
ZipCPUI usually catch errors like these using Verilator--even if I don't synthesize with Verilator11:59
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promachnow, I really like verilator linting feature12:04
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ZipCPUWhy, did you find your bug?12:12
promachZipCPU: verilator linting provides some other insights into my coding12:15
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FL4SHKVerilator is really high quality software14:16
FL4SHKI've honestly considered switching to it for when I just need a simulator.14:17
FL4SHKIt's le fast14:20
FL4SHKI'm surprised that GHDL is a GCC front end....14:21
FL4SHKHoly crap is that cool14:21
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