Sunday, 2019-04-14

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FL4SHKwhat is the state of VHDL support in Yosys?15:45
FL4SHK"nonexistent" is my guess.15:45
FL4SHKlooks like it requires verific15:49
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corecodeFL4SHK: what are you up to?15:58
FL4SHKEvaluating my options.16:00
FL4SHKI'm pretty happy with VHDL itself...16:00
FL4SHKI just hate classical Verilog16:00
FL4SHKI really like SystemVerilog and VHDL.16:00
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tpbTitle: VHDL frontend efforts · YosysHQ/yosys Wiki · GitHub (at
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cr1901_modernghdlsynth isn't feature complete, but has meaningful yosys support. The NVC simulator is feature complete but doesn't have meaningful yosys support; the idea would be to generate yosys RTLIL from NVC.16:51
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FL4SHKoh hey, cr1901_modern, do I know you?17:12
FL4SHKlooks like you're in at least one other channel I'm in...17:12
FL4SHKvup2, cr1901_modern :  any way to use the yosys formal verification with that?17:13
daveshahI don't think either of those frontends support assert or PSL17:19
daveshahSo your properties would have to be in SV17:19
FL4SHKOkay.  Is that a big deal?17:19
FL4SHKI'm honestly just trying to figure out my best option going forward at this point.17:20
FL4SHKI think I'd prefer to just stick to SystemVerilog.17:20
FL4SHKnow... I'd like to improve the yosys read_verilog -sv interface support17:21
FL4SHKit just... doesn't seem to support passing a parameter into an interface17:21
FL4SHKthis is such a glaring issue17:21
FL4SHKeven without the localparam being in package, it doesn't work.17:22
FL4SHKit also doesn't seem to think the parameters of an interface are constant?17:22
FL4SHKsuch that, in that "Adder" module, I couldn't access the parameters of the interface that was passed in17:23
FL4SHK"couldn't detect width of signal"17:28
FL4SHKor, "Failed to detect width for parameter"17:32
FL4SHKappears to be a bug in evaluation of parameters inside packages?17:34
daveshahYes, that looks like a bug17:43
daveshahalso seem to have it some kind of issue in the frontend debugging, -dump_ast2 which usually helps with this kind of stuff is hitting an assert fail17:43
FL4SHKI'm gonna try to fix thi17:44
daveshahthat would be great17:47's in "type2str"17:50
FL4SHKapparently it's an AstNodeType with value 9517:51
FL4SHKwhich is just...17:51
FL4SHKhow do I do debug build?17:51
FL4SHKI believe I found the thing to do with the makefile.17:53
FL4SHKmake ENABLE_DEBUG=1 looks like it17:53
FL4SHKI was afraid of digging into this yesterday... but now I think I'm going to give it a shot17:57
FL4SHKoh, you know what that ast assert bug appears to be?18:01
FL4SHKLooks like there was no update of the X macro in type2str18:01
FL4SHK...could stand to have a list of things there tbh18:02
daveshahYes, that makes sense18:20
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FL4SHKOkay, I think this is too tough for me18:37
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davoshey all. I'm not able to get yosys to infer an SB_SPI. I have to add a (* keep *) tag to the module instance, for it to be inferred, so something is not quite right. I'm using an iceup5k-sg48. Im not seeing any warnings from yosys, it seems to silently optimize away the block, but I could just not be reading the yosys output correctly. Any recommendations on how to debug the issue further? the sb_spi is being used as a slave, im not20:50
davoseven connecting a miso line, just SCK, SS, and MOSI, along with the internal SB ports.20:50
daveshahdavos: it will only be optimised away if none of its outputs (including the system bus outputs) are used21:04
daveshahMost likely because other logic is being optimised away21:04
daveshahLooking for the names of the wires connected to those ports in the Yosys log output might help to debug this21:06
davosok, thanks, thats a good sanity check. Its probably due to how im crossing the clock domain, from spi to rest of the logic; still new at this. for instance SCKI is 6mghz and SBCLKI is 12 mghz21:11
davosactually, the SB_SPI should cross the clock domain for me... i think. i get what your saying, is there a way to have yosys optimize my logic LESS aggressively?21:19
tntdavos: post your code somewhere21:28
davosim gonna fight with it for another round first haha. Ill be back later with either a KO or a code post. daveshah's comment narrows it down pretty well21:35
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