Saturday, 2019-04-13

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FL4SHKIt just... appears that they're not with the version I got from GitHub00:01
FL4SHKI get a lot of00:02
FL4SHKWarning: Identifier `\MyInterfaceInstance.mysig_out' is implicitly declared.00:02
FL4SHKthings like this ^00:02
FL4SHKand then it treats them as 1-bit things.00:03
FL4SHKmaybe I'm not running the right commands00:10
FL4SHK"failed to detect width for identifier"00:16
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FL4SHKit appears that I've found a bug00:33
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tpbTitle: [VeriLog] module top(BTN1, BTN2, BTN3, LED1, LED2); input BTN1, BTN2, BTN3; output L - (at
tntAt line 6, is that valid in verilog ?!?12:55
corecodethe initializer12:55
tntLED are the outputs12:56
corecodethen i don't understand what this is supposed to do12:57
tntwell my guess is the author just assumed it woudl 'connect' Sum[0] with LED1 'bidirectionally'.12:57
tntlike a physical wire ...12:58
corecodei see12:58
tntbut afaik ... it's wrong.12:58
corecodeyes, that seems wrong12:58
tntand yet yosys seems to accept it.12:59
corecodeit looks like an initializer12:59
daveshahYosys and LSE both seem to treat the = as bidirectional, Synplify and Verilator seem to treat it as unidirectional12:59
corecodeoh interesting13:00
corecodei mean it doesn't make much sense to use an output as RHS?13:00
tntI usually try to avoid it ...13:04
tntI know in VHDL it's just forbidden.13:04
corecodethe standard calls this net_decl_assignment13:05
corecodeand it's in the 6.1 continuous assignment section13:06
corecodeso that means there are two continuous assignments13:07
tntyeah and the way I read it, it's clearly unidirectional. Value is _driven_ on the LHS whenever the RHS _changes_.13:09
corecodecan an output port be readable?13:10
tntI'm trying to find that in the spec right now.13:11
corecodethere are examples that imply that you can use output ports as RHS13:17
corecodei think it matters only for the module using the submodule13:18
tntyup, afaict they are just normal wires so you can 'read' their values.13:19
corecodeso in this case, the problem is that there are two conflicting continuous assignments13:20
corecodeand something bidirectional going on as well?13:20
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FL4SHKDid anyone happen to see what I mentioned last?16:43
FL4SHKI think I found a bug in yosys's SystemVerilog support.16:43
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FL4SHKwell, I've made a fork.  I'll see if I can fix it myself.18:08
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