Friday, 2019-04-12

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litghostdaveshah: I haven't seen any activity on , is it in an acceptable form?00:02
tpbTitle: Add additional cells sim models for core 7-series primitives. by litghost · Pull Request #928 · YosysHQ/yosys · GitHub (at
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mithroWhy do some of the D flip flop models start with $_DFF and some start with $__DFF ?02:26
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daveshahlitghost: I've just asked Eddie to review08:26
daveshahmithro: the $_ cells are "first class" gate-level cells that are supported throughout Yosys (eg for abc, opt, etc) whereas $__ cells are special-purpose cells08:27
daveshahThe $__ cells are generally only supported between one or a couple of passes and intended to be short-lived intermediate cells08:28
daveshahThe intention being you would then techmap them to arch-specific cells08:28
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litghostdaveshah: Thanks!  I have trouble knowing who should be notified to take a look at reviews15:09
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mithrodaveshah: Is this a liberty file? -> ?20:44
tpbTitle: yosys/cells.lib at master · YosysHQ/yosys · GitHub (at
daveshahmithro: yes20:45
mithrodaveshah: Do you have a reference on how a liberty file works? I'm trying to understand what the function: "IQ" and ff(IQ, IQN) {} bits work?20:47
daveshahmithro: maybe have a look at
mithrodaveshah: Had that doc already open -- it only has one reference to "function:"... -- the ff Group section seems to have some of what I'm after but it is not the clearest.... Most of the docs I have so far are more interested in things like temp, voltage, process, etc...20:59
mithrodaveshah: Looks like might be a good reference...21:02
daveshahff(IQ, IQN) defines a flipflop with non-inverting output variable IQ and inverting output variable IQN21:02
daveshahnext_state specifies that the state after a clock edge is D21:03
daveshahfunction gives the logic function for a pin21:03
daveshahfunction: "IQ" means the pin simply mirrors the IQ variable (ie the FF state)21:03
daveshahalso FYI, you can combine read_liberty and write_verilog to convert liberty to verilog with Yosys21:04
mithrodaveshah: Is there a write_liberty?21:05
daveshahIt's not something anyone has had a use case before21:06
daveshahA simple implementation probably wouldn't be too hard21:06
mithrodaveshah: Does adff means async dff? ->
tpbTitle: yosys/adff2dff.v at master · YosysHQ/yosys · GitHub (at
mithrodaveshah: So that is an Async DFF to Sync DFF techmap?21:10
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mithro daveshah: eddie mentioned that ASIC designers mainly use liberty files for timing - does yosys already read timing information from liberty files at all?21:32
daveshahmithro: No, but abc does (when used with Yosys it takes a liberty file directly rather than going through read_liberty)21:35
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mithrodaveshah: looking at module \$__DFFS_NN0_ (input D, C,    R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"),   .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE"))  _TECHMAP_REPLACE_ (.CLK(C),         .LSR(!R),   .DI(D), .Q(Q)); endmodule22:22
mithrodaveshah: Doesn't that have 1 to many values in the flip flop name?22:22
mithroWhat are the 3 values for?22:23
daveshahNegative clock, negative set/reset, reset22:23
mithrodaveshah: The reset == value when negative set/reset occurs?22:24
daveshah$__DFFS is a special synchronous set/reset DFF used by dff2dffs and the ECP5 techmap rules only22:26
FL4SHKso, I'm looking at the yosys GitHub README22:26
FL4SHKthe supported features of SystemVerilog lists interfaces... and modports22:27
FL4SHKbut it doesn't seem to synthesize the use of those features as module ports?22:27
FL4SHK(yes, I know I've talked about this multiple days in a row now)22:27
mithrodaveshah: and $__DFFE_NN0 is the async set/reset version?22:28
daveshahYes, also with enable22:28
daveshahFL4SHK: have you looked at the interface tests? Eg
tpbTitle: yosys/ at master · YosysHQ/yosys · GitHub (at
daveshahI don't know much about SV interfaces, so can't help much more than that22:29
mithrodaveshah: $__DFFE_NN0- Clock Negative, Enable Negative, Set/Reset - ???, Value on Reset 0 ??22:30
daveshahNegative clock, negative set/reset, positive enable22:31
mithrodaveshah: the ECP only has positive enables?22:31
FL4SHKdaveshah:  wait22:31
FL4SHKmaybe I did something wrongly!22:31
FL4SHKnow I've got to give it a try again22:31
daveshahmithro: No, but Yosys only supports positive enables iirc22:31
mithro$_DFFE_PN_ (D, C, E, Q) - A positive edge D-type flip-flop with negative polarity enable. ?22:32
daveshahAh, looks like it only supports them without set/reset22:33
FL4SHKdaveshah:  you may have made my day22:33
FL4SHKthank you :P22:33
FL4SHKthat example is EXACTLY what I was looking for22:33 can I contribute more?22:33
FL4SHKer, how can I contribute to yosys?22:33
daveshahFL4SHK: is there anything in particular you want to work on?22:34
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FL4SHKtypedef, struct, enum22:34
daveshahAll of those would be great contributions22:34
FL4SHKI've been working on my own compiler thing22:34
mithrodaveshah: I'm trying to build a table of flip flops at
tpbTitle: Flip Flops - Google Sheets (at
FL4SHKbut contributing to yosys may actually be a better idea22:35
daveshahmithro: DFFS/DFFSE are sync22:36
daveshahDFFSR have both an async set and reset (and consequently don't map to most FPGA arches)22:36
FL4SHK...I do wish you could parameterize structs, btw22:36
FL4SHKoh, yeah22:37
FL4SHKone other thing:  `type`22:37
FL4SHKthat's one thing that would be... useful22:37
mithrodaveshah: So, $_DFFSR_ should be async?22:37
daveshahmithro: yes22:37
tpbTitle: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at
mithrodaveshah: Is it when there is a 0 or 1 in the truth table that it is async?22:39
daveshahOr just look at the sensitivity list22:39
mithrodaveshah: It is async if both the clock and reset signal is in the sensitivity list?22:41
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FL4SHKIs the open source form of yosys used for commercial applications, or do companies generally want to use the commercial version?22:54
daveshahDepends what people are doing22:55
mithroFL4SHK: Also depends on how you defined "commercial applications"22:55
daveshahI know quite a few commercial users of open source Yosys (eg because they want a fully open flow)22:55
daveshahOthers need full VHDL and SV22:55
FL4SHKI do FPGA dev professionally... and I'm concerned about there being a conflict of interest22:56
FL4SHK...don't want to lose my job22:56
daveshahProbably fine if you don't work for a company that writes HDL frontends22:57
FL4SHKI don't22:57
daveshahBut do check your T&Cs22:57
FL4SHKI think I'm safe to *use* yosys, at least22:57
daveshahThe one thing to avoid is benchmarking - particularly publicly - against anything commercial you have at work22:58
daveshahThat's almost always banned in the EULA22:58
FL4SHKI don't think I can even install yosys at work22:59
mithroFL4SHK: You would have to ask your companies legal council - generally though the software is under a *very* permissive license22:59
daveshahYes, we don't require copyright assignment or anything like that22:59
FL4SHKcould we consider the version of SystemVerilog that the open source version of yosys implements to be a "custom language" on account of it not being anywhere near complete?23:00
FL4SHKbecause... I may be safe, then23:00
mithroFL4SHK: Google has released their "best practice for compliance with open source licenses" you can read if your interested ->
tpbTitle: Licenses – (at
FL4SHKmithro:  it's actually not the open source licenses I'm concerned about23:01
daveshahFL4SHK: well, Yosys does have a few non-standard extensions mostly for formal23:02
FL4SHKor, at least for the Verilog side, anyway?23:02
FL4SHKwith -sv, isn't the formal stuff a subset of what SystemVerilog has?23:02
mithrodaveshah: _SR_ flip flops would be considered Async as they don't have any clocks, right?23:03
daveshahYes, it also adds a few convenience things like $anyseq, $anyconst23:03
FL4SHKI think I'm at the very least safe to *use* yosys23:03
FL4SHKso even if I don't end up contributing... hmmm23:04
daveshahmithro: yes, although a latch might be a better description than a flipflop23:04
FL4SHKlatches are normally banned outside of ASICs, eh?23:04
daveshahAlthough there is some interesting research opportunity into doing fully async stuff with FPGAs23:05
FL4SHKI didn't know that was happening.23:05
daveshahIt's not something you want to do unless you know exactly what's going on23:05
FL4SHKUh, right23:05
daveshahFPGAs aren't glitch free in general23:05
FL4SHKI've heard of async processors before.23:05
mithrodaveshah: I  actually talked to some people at Archonix yesterday23:05
mithrodaveshah: They got out of the async FPGA game in the end :-(23:06
daveshahAh, that's a shame23:06
daveshahI know a few people at my university are vaguely interested in async stuff23:06
FL4SHKI think I will hold off on attempting to contribute to yosys for now.23:07
FL4SHKbut if someone else could... implement `typedef` and `enum`, I'd probably be really happy23:07
FL4SHK`struct`s are FAR less necessary when you have `interface`s.23:08
FL4SHKoh, here's a question I had:  can yosys handle arrays on ports?23:08
FL4SHKfor -sv23:08
mithroFL4SHK: There are quite a few people interested in support for those features... I think someone was even working on enums?23:08
FL4SHKI can probably just wait for them to be implemented?23:09
FL4SHK...I'm shocked that `interface`s are, by the way, but pleasantly so.23:09
FL4SHKI've been dying to be able to use `interface`s in formal23:09
FL4SHKand in design23:10
FL4SHKI was previously using Icarus Verilog to convert *its* subset of SystemVerilog into Verilog.  That's how I originally did formal verification.23:10
mithrodaveshah: You aren't making it to latchup right?23:12
daveshahNo, exams :(23:12
mithrodaveshah: You have exams with a masters program? Or hasn't that started yet?23:14
daveshahIt's a integrated masters MEng23:14
daveshahSo 4 years with no bachelors23:14
mithrodaveshah: Ahh23:14
FL4SHKWhat are you doing your master's in/23:15
daveshahElectronic and Information Engineering23:15
FL4SHKah.  I have a bachelor's in mechanical engineering, and a master's in electrical engineering.23:15
FL4SHKI just got the master's in December.23:15
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mithroWhat would you call "sync verse async" ?23:33
ZipCPUAsync FF: always @(posedge i_clk, posedge i_reset) if (i_reset) Q <= 0; else Q <= D;23:35
ZipCPUSync FF: always @(posedge i_clk) if (i_reset) Q <= 0; else Q <= D;23:36
mithroZipCPU: I mean - like "Execution mode" or ?23:36
ZipCPUI must be missing something.  What "execution mode" are you talking about?23:36
mithroZipCPU: A flip flop can be sync or async right? What would you call this property of a flip flop?23:37
ZipCPUYes, I would call that a property of the flip flop23:38
mithroZipCPU: Yes but what is the name of this property of the flip flop? :-P23:38
ZipCPUUsually its the "synchronous or asynchronous reset" proeprty23:38
ZipCPU... or some such23:38
ZipCPUSome FF's also have an asynchronous set property as well23:38
FL4SHKdaveshah:  so, out of curiosity, do interfaces instantiated in other interfaces work in yosys?23:48
FL4SHKalso, is there an option I need to set to make interfaces actually, uh, compile?23:58
FL4SHKcompile correctly*23:59

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