Friday, 2019-03-15

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corecodewow, on the ecp5 my cpu also only does 44MHz02:16
corecodei guess i have a shit design02:16
sorearwhat are you comparing to?  what's your goal?02:23
corecodecomparing to u4k02:24
corecodewhere i get 29MHz02:24
corecodesorear: my goal is to improve my design :)02:24
sorearrough specs ? critical path ?02:24
corecodeseems to be related to instruction fetch going through some MUXes02:26
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emeb_maccorecode: have you tried checking the max freq of your CPU design using icecube?03:16
emeb_mac(just for comparison to FOSS tools)03:17
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daveshahcorecode: switching to the faster ECP5 (normal -8 speed grade or 5G variant) should make a big difference09:09
daveshahThe tools for the ECP5 aren't as optimised yet either09:09
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sxpertdaveshah: ok. manage to get the placer to compile. had to redo the CMake10:18
sxpertdaveshah: ok, it seems to work as advertised. design is even faster than before10:25
daveshahYeah, the new placer does tend to improve ECP5 quality of results10:27
sxpertlooks like the generated bitfile doesn't work though10:27
* sxpert tries again10:27
daveshahSounds like something marginal might be going on10:29
sxpertah, getting "2 warnings, 1 error"10:32
sxpertERROR: unsupported frequency unit 'MHZ'10:32
sxpertWarning:     ignoring unsupported LPF command 'BLOCK RESETPATHS'10:33
sxpertWarning:     ignoring unsupported LPF command 'BLOCK ASYNCPATHS'10:33
daveshahThe warnings don't matter10:34
sxpertthe error however ?10:34
daveshahThe frequency bug was fixed on master but not merged into that branch10:34
daveshahJust change MHZ to MHz10:34
* sxpert tries again10:36
sxperttons of "Unmatched LPF" warnings, but I suppose that's because I don't use them10:40
sxpertno more errors10:40
sxpertlets program the thing in the chip10:41
sxpertok, it now works10:41
sxpertdoes what it should10:42
daveshahThe unmatched warnings are also solved in master10:44
daveshahOut of curiosity, what freq are you getting now?10:44
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sxperthah, looks like we will get rectangles, no more fpga art10:48
sxpertInfo: Max frequency for clock '$glbnet$clk_25mhz': 70.67 MHz (PASS at 25.00 MHz)10:51
sxpertbefore routing :10:51
sxpertInfo: Max frequency for clock '$glbnet$clk_25mhz': 40.46 MHz (PASS at 25.00 MHz)10:51
daveshahYeah, the pre routing delay estimates need tuning10:52
daveshah70MHz is pretty good, what was it before10:53
sxpert65 or so10:53
sxpertthe design seems pretty fast for such a complicated beast10:53
sxpertstill complains about the rom_data10:54
daveshahYeah, part of the problem is just ECP5 BRAMs being fairly slow - combined with such a big RAM being spread all around the chip10:56
daveshahThe BRAMs on the ECP5-5G parts are about 3x faster than the -6 grade normal past10:56
sxpertam about to add some more, hah !10:56
sxpertI have to add 64 BRAMs for the system ram10:57
daveshahUnlikely to make the design any slower - each clocked RAM starts a new timing path, so to say10:57
daveshahIt would be interesting to see how making the main ROM smaller changed Fmax10:58
sxpertwell, the main issue is that the rom jumps to 7xxxx on the 11th instruction ;-)11:05
daveshahIt doesn't need to work11:09
daveshahwould just be interesting to see how it changes things...11:09
sxpertah I see11:10
sxpertjust a compile11:11
sxpertI can probably do that11:11
sxpertsay, 1 bram worth ?11:12
sxpertok so 1 bram is 16Kb, that's 2**12 nibbles11:16
sxpertI have the system ram in, all 64 brams of it11:17
sxpertand 1 bram for rom11:17
sxpertdaveshah: the next thing I want to tackle is the debugger string generation, seems suboptimal, generate ffs instead of brams11:19
daveshahsxpert: sure, where is the code for that11:19
tpbTitle: hp-saturn/saturn_debugger.v at fix_rom_read · sxpert/hp-saturn · GitHub (at
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daveshahsxpert: I'm afraid that's a bit ambitious11:21
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daveshahan intermediate write data and write enable register would be more likely to work11:21
sxperthah !11:21
sxpertso have an 8 bit byte reg, and write to the memory in another domain ?11:22
sxpertwith only one rom bram, I get Info: Max frequency for clock '$glbnet$clk_25mhz': 75.16 MHz (PASS at 25.00 MHz)11:23
daveshahIs the critical path still the ROM?11:24
* sxpert added the sysram11:24
sxpertdaveshah: I get this :
tpbTitle: Info: Critical path report for clock '$glbnet$clk_25mhz' (posedge -> posedge): - (at
daveshahLooks like system RAM has taken over now11:29
daveshah(26,82) -> (27,27) is a long wire11:29
sxpertI see11:30
sxpertguess I could use some registers or something11:30
sxperton reading and writing11:31
sxpertfor the rom, I pre-read on phase 0, then dump that on phase 1 to the bus11:31
sxpertguess I could do the same for the ram11:31
corecodeah, it was 44 pre route, 61 post route11:33
corecodeand with -8 68 pre route, 85 post route11:33
daveshahthat makes much more sense11:34
daveshahwhat if you try a 5g part (--um5g-45k)11:34
daveshahthey have much faster block RAMs11:34
corecodei thought they're all the same die11:35
corecodeoh yea11:35
corecode120 pre, 120 post11:35
daveshahthe 5g parts run at 1.2V rather than 1.1V11:35
* sxpert would love an ULX3S++ with an 85FUM5G ;-)11:35
daveshahthis makes a big difference11:35
sxpert47€ a piece on mouser !11:39
sxpertnot too bad11:40
sxpertthe evn board is 86 eur11:40
daveshahyeah, the evn board is very good value for money11:40
daveshahonly problem is it has no external RAM :(11:40
sxpertthat's a problem11:41
sxpertall depends on the system flash though. I could do with the system rom in the flash11:50
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sxpertdaveshah: ok, ram accesses are now pipelined13:26
sxpertInfo: Max frequency for clock '$glbnet$clk_25mhz': 72.06 MHz (PASS at 25.00 MHz)13:26
sxpertrom still shows up as the biggest delay13:26
sxpertnot a big issue though13:27
daveshahwhat does --um5g-85k give?13:28
daveshahI guess this is much faster than a real Saturn?13:28
sxpertthe real saturn ran at 4MHz13:31
sxpertalso, I seem to be able to implement things in less cycles than the original13:32
daveshahCould you make an upgrade board for calculators with an ECP5 on?13:32
daveshahMight need a bigger battery too13:32
daveshahthat would be really awesome13:32
sxpertreplace those 3x AA with lipo13:32
sxpertor was it AAA13:32
sxpertyeah, 3x AAA13:32
sxpertblast the TIs out the water ;)13:33
sxpertthe original idea was to build one with a giant led screen13:34
sxpertso, with all basic modules setup, am going at 70Mhz or so13:36
sxpert(rom, mmio, ram)13:36
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sxpertnow, just need to fill in alu based instructions13:37
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sxpertdaveshah: on the um5g-85k part: Info: Max frequency for clock '$glbnet$clk_25mhz': 108.05 MHz (PASS at 25.00 MHz)14:00
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MoeIcenowydaveshah: I think a Saturn emulator on ARM920T is faster than real Saturn14:21
MoeIcenowy(I have such an emulator14:21
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sxpertMoeIcenowy: indeed, an emulator on an arm is faster, but it's not the same thing14:29
sxpertfor instance, you can't do grayscale display14:30
sxpertalso, that's no fun ;)14:31
sxpertthe fun part is, I may also implement the instruction added in that emulator ;-)14:37
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sxpert(all those 80Cblah instructions)14:42
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MoeIcenowysxpert: I only bought a 39gs because it's dirty cheap15:36
MoeIcenowysxpert: in fact I wonder why don't they add some "execute raw ARM code" instruction ;-)15:41
somlodaveshah: is there a branch on github for the "stable" trellis? ( Do you have version numbers anywhere that I should "bump" (from "0.0") before I open a bugzilla ticket for submitting to Fedora ?15:52
daveshahsomlo: It's a git tag, 1.015:53
somlooh, so I'll actually have to clone the repo before I can see it :) Thanks!15:53
daveshahYou can get it on github too15:54
tpbTitle: GitHub - SymbiFlow/prjtrellis at 1.0 (at
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sxpertMoeIcenowy: there is16:20
sxpertMoeIcenowy: the main issue with those is that the keyboard is chicklet and pretty bad16:21
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MoeIcenowydaveshah: BTW why does icestorm have no version number?17:28
daveshahgetting clifford to do proper releases is always hard17:29
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somlofedora review request for trellis:
tpbTitle: 1689397 Review Request: trellis - Lattice ECP5 FPGA bitstream creation/analysis/programming tools (at
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soreargonna try to get that in #fedora-riscv? :D20:02
somloyeah, that's the plan -- find/buy (or, worst case, design/build) a dev board with 2GB RAM and an 85k 5g ECP5 chip, build a rv64gc based SoC that can boot Fedora (similar to lowRISC), then we'd have a self-hosting computer (that can not only rebuild its own kernel, but also its own *hardware*) :)20:06
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sxpertsomlo: can you self-update the flash and reboot the fpga ?21:06
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somlosxpert: I think that depends on the particulars of the (at this point, theoretical) development board22:49
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