Thursday, 2019-03-14

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promachDoes yosys support systemverilog "inside" keyword yet ?02:57
promachseems like yosys does not support fully "inside" keyword, same problem here with
tpbTitle: AR# 64777: Vivado Synthesis - System Verilog case inside range expression support (at
promachdaveshah : have you encountered such situation previously ?03:17
promachI have set up a small test code that illustrates the problem03:21
tpbTitle: System Verilog case inside range expression support : yosys (at
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somlodaveshah: the trellis versa5g soc example gets a 50MHz clock with the non-default (w.r.t. yosys/ecp5/cells_bb.v) settings of .CLKI_DIV(2), .CLKOP_DIV(12), .CLKOP_CPHASE(11).  For a 10MHz clock (for the rocket chip), you got Diamond to come up with .CLKI_DIV(10), .CLKOP_DIV(65), .CLKOP_CPHASE(64).12:37
somloTurns out, on a *real* 5g ecp5 the rocket chip can go as fast as 24MHz. I get CLKI_DIV (would need 5 for 20MHz), but what about CLKOP_DIV and CLKOP_CPHASE?12:37
somloecppll generates 10 and 50 MHz pll settings that are pretty radically different from the working ones we're currently using, so I'm wondering if there's just more than one canonical way to set the pll to generate a given frequency, or what...12:38
daveshahThere are different feedback path options, which are the main difference12:38
daveshahThe important thing is to keep the VCO in its 400-800MHz range12:39
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somloecppll also generates different ICP_CURRENT and LPF_RESISTOR values (12, 8) vs. what's in the working examples (6, 16) respectively. Should I worry about that ? :)13:01
sxpertdamned, things that work in simulation, and miserably fail on chip13:04
daveshahNo one has figured out the algorithm to determine those values ye513:27
daveshahThey don't seem to be critical, just optimising lock time and jitter I think13:27
somloso the 20MHz clock as generated by ecppll seems to work (blinking twice as fast now :) )13:28
somlonextpnr *sometimes* meets >= 24 MHz, but not always, so I think I'll stick with 20 for now...13:29
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MoeIcenowysomlo: I think you can try to run a for loop to get nextpnr to try to meet 24MHz ;-)17:33
tnt(changing the seed ...)17:33
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somloMoeIcenowy: if at first you don't succeed... :D18:06
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MoeIcenowyI remember the Supra tool from AGM have such a function to run for a loop to reach timing18:19
tntMulti Pass Place and Route is/was in Xilinx tools as well.18:20
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corecodei should install trellis and figure out how fast my cpu can run on an ecp521:36
sxpertmine looks like it can do 50MHz easily, on the good compilation days21:50
corecodeand on the ice40?21:51
sxperthaven't tried for a while21:51
sxpertneed to update the script21:51
sxpertat this time it wouldn't fit in the ice40, am using up all of the brams for rom and ram ;-)21:52
sxpertthat is 192 of them ;-)21:52
sxpertand only 1/2 the system rom ;(21:52
sxpertlast run, 36Mhz prior to routing, 65.66 after21:53
corecodewow, it sped up21:53
sxpertyeah, it moves randomly21:53
sxpertwith me adding stuff ;-021:54
sxpertbeen re-writing from march 6, had some wierd behavior that I couldn't fix21:54
corecodeso i want to build a generic debug adapter, which means mostly bit wiggling in different ways, and different control flows; i wonder whether i should try to avoid a mcu and do it in fpga21:55
sxpertso, branched from there, and slowly re-adding the bits from master21:55
sxpertok, time to head to bed21:57
sxpertenough hadking for the night21:57
sxpertah no, one more thing I need to check21:58
sxpertthen commit and push21:58
sxpertcompiling the design takes a good 10mn21:59
daveshahsxpert: did you try the new placer?22:02
sxpertdaveshah: nope22:02
sxpertis it out yet ?22:02
daveshahIt's still not upstream22:02
daveshahBut on a pull request22:03
tpbTitle: HeAP-based analytical placer by daveshah1 · Pull Request #219 · YosysHQ/nextpnr · GitHub (at
sxperthow does it apply to a head tree ?22:04
daveshahgit remote add daveshah1 && git pull daveshah1 && git checkout placer_heap22:06
tpbTitle: GitHub - daveshah1/nextpnr: nextpnr portable FPGA place and route tool (at
daveshahShould do it22:06
sxpertthen make clean && make22:08
daveshahYou'll also need to install eigen322:10
daveshahlibeigen3-dev on ubuntu22:11
sxpertok, installed just in time before it has a chance to barf ( while it is building chipdb-85k.bba ;-) )22:12
sxpertah, latest run 69.00 MHz22:12
sxpertI only removed a couple ifs that were doing the same thing !22:13
corecodeif they do the same thing, they get optimized away22:13
sxpertsomehow something did something different ;-)22:13
daveshahMost likely enough to change ordering of nets and cells, if nothing else22:14
daveshahThat will result in a totally different initial placement22:14
sxpertI see22:15
sxpertso it's mostly random, there's no method to this madness ;-)22:15
sxpertok, so baseline nextpnr generate something that is verified to work22:17
daveshahYou can always peturb the placement and routing with the --seed parameter to nextpnr22:18
sxpertdaveshah: according to the pr page, there is still an issue compiling on ubuntu 16.0422:18
daveshahNo, that's a regression test failure22:19
daveshahIt's a design that fails sometimes on master too22:19
sxpertah !22:20
daveshahThe test needs looking at properly22:20
sxpertsomehow at the limits of whatever it's trying to do ?22:20
sxpertah the test is somewhat b0rk, that will do it ;)22:20
sxpertsometimes it fits in, sometimes it randomly can't22:21
sxpertI see22:21
somlore. PR #219, if any of you have a Fedora box laying around this is what I'm using:
tpbTitle: Index of /~somlo/nextpnr-rpm (at
* sxpert hopes to never have to run yosys and nextpnr on his Sparcstation V ;-)22:39
* sxpert also hopes nobody attempts a port on vax ;-)22:40
sxpertit takes like 30mn to compile on a 4 cores laptop with 16G of ram ;-)22:52
sxpertand your average design take 10mn or so on the same machine22:52
sxpertnow imagine on a 1MHz vax ;-)22:52
FL4SHKyes, formally verify on a 1 MHz machine22:53
sxpertinsert <2000 years later> card from spongebob squarepants22:54
FL4SHKOLD freaking episode22:54
sxpertwhy does make install rebuilds the bba files ?23:04
daveshahProbably a bug23:09
sxpertdaveshah: also it looks like the work is done twice23:25
sxpertah, looke like "make", followed by "sudo make install" rebuilds everything23:28
sxpertok, all compiled and installed (including new trellis and yosys)23:33
sxpertdaveshah: hmm23:36
sxpertInfo: Running simulated annealing placer.23:36
sxpertis there an option I need to pass in ?23:36
daveshahDid it run HeAP first?23:37
sxpertdid initial placement, then this one23:37
daveshahDid it print out anything about solving or spreading?23:38
sxpertnot that I can see23:38
daveshahSounds like it didn't build the new placer23:39
daveshahIt should be the default for ECP523:39
sxpertnextpnr-ecp5 -- Next Generation Place and Route (git sha1 4c73061)23:39
sxpertis the version I have23:39
daveshahCan you post the full --help23:40
tpbTitle: nextpnr-ecp5 -- Next Generation Place and Route (git sha1 4c73061) General op - (at
FL4SHKyosys doesn't do place and route, does it?23:41
daveshahsxpert: there should be some new options, including --sa-placer to switch to the old placer, in there23:42
FL4SHK...I've only used yosys for formal verification myself23:42
sxpertdaveshah: should I have re-run configure or whatever it is ?23:43
daveshahsxpert: rerunning CMake shouldn't be needed in this case23:43
daveshahIt certainly wouldn't cause this problem23:43
daveshahWhat does is the last commit in git log in nextpnr23:43
sxpert placer1: Only get criticalities when in timing-driven mode23:43
sxpertI notice23:44
sxpert    A CMake option 'BUILD_HEAP' (default on) configures building of the23:44
sxpert    HeAP placer and the associated Eigen3 dependency.23:44
daveshahCommit sounds correct23:44
daveshahThat option is default on, so it should be fine23:44
daveshahEven if it was turned off, that command line help still isn't correct23:45
sxpertwell, bedtime here23:47
sxpertsee you tomorrow23:47

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