Wednesday, 2019-03-13

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emeb_macquestion on nextpnr-ice40: trying to use an instance of SB_PLL40_CORE with reference clock originating on-chip in the 48MHz HF osc. Yosys runs OK but nextpnr gives me an error: ERROR: PLL 'pll_inst' couldn't be placed anywhere, no suitable BEL found.05:20
emeb_macThis is on a up5k design with clock originating on-chip (not coming from an IO pad)05:21
emeb_mac(reference clock that is)05:21
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corecodehm, why can't it place it10:51
tntI made a test case and it works for me.10:59
tntSo I'm waiting from him to come back and post a snippet of what he's doing ...11:00
daveshahmaybe pin 35 is being used and blocking the pll11:09
tntOh yeah, right, that's probably it.11:12
corecodesay what?11:12
daveshahcertain pins can only be used as outputs when the pll is used11:12
tntPLL input path is shared with the IO input path of the IO tile it's in.11:12
corecodeso the pll is a padin, not a gbufin?11:13
corecodealready forgot again11:13
corecodethat seems dumb11:13
daveshahlikewise PLLOUTCORE{A,B} use the D_IN_0s of the IO tile they are in11:13
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emebJust read the channel log - saw the advice on pin 35 vs PLL. Thanks for that - I'll check if moving I/O around in the .pcf helps.16:33
emebYes - I did have pin 35 defined as input and freeing it up allowed the PLL to be placed.16:40
emebUnfortunately, I'm using a upduino V1 for this test and the mistakes in the board design WRT the PLL supply seem to be preventing it from working.16:48
emebWell, I've got my own boards waiting to be built with proper PLL supply ckts. Will have to wait for those.16:49
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tntemeb: if you have a bit of wire, you can 'fix' it  :p16:55
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emebtnt: yeah, I could. but, #effort. :)17:00
emeblol - routed the PLL clock output to a pin and put it on the 'scope.17:02
emebsuch jitter!17:02
tntoh really ? I guess it's not locked right ?17:03
MoeIcenowyI think the internal OSC itself is weird17:03
MoeIcenowyupduino v1... weird board17:04
MoeIcenowyit's even worse than designing one by yourself17:04
MoeIcenowy(recently I purchased a UPduino before I started my own UP5K board, and received it after finished the sample17:05
MoeIcenowy(then I regretted to purchase the UPduino17:05
MoeIcenowyalthough it's v217:05
emebI'm trying to make a 16 MHz clock from the on-board 48MHz with the PLL. The actual output freq is about 1.2MHz and very wiggly.17:05
MoeIcenowyemeb: why not use DIV?17:05
MoeIcenowy16 = 48 / 317:05
MoeIcenowyadd #(.CLKHF_DIV("0b10")) to the SB_HFOSC17:06
tntMoeIcenowy: I think div only does 48 24 12 6 ...17:08
emeb16 is not an option17:09
emebI actually have a /3 circuit stubbed in for now17:09
corecodethat hfosc is probably not very good17:09
emebbut only 33% duty cycle, so I wanted to try the PLL17:09
corecodelooked jittery to me17:09
MoeIcenowyoh forgot it17:09
MoeIcenowyhow to mod my brain to have an ECC memory?17:10
corecodemore system 217:10
corecodeoperate as if you are likely to make mistakes17:11
emeb16MHz output derived from 48MHz HFOSC ->
tpbTitle: Dropbox - 0313191108.jpg (at
emeb(apologies for shakycam)17:21
emebbut yeah - very jittery.17:21
MoeIcenowyemeb: what board?17:21
emebonly ~45dB down skirts @ 100kHz. nasssty.17:24
MoeIcenowyv1 or v2?17:24
MoeIcenowythe PLL supply of v1 is quite weird17:24
emebwell, it's just plain wrong and I can't get the PLL to lock. This pic is just the HFOSC17:25
emebno PLL17:25
MoeIcenowyemeb: how about raw 48MHz output?17:28
emebwouldn't expect it to be any different. Dividers don't alter jitter.17:30
emebHere's the direct output from the 48MHz HFOSC with a bit more processing on it:
tpbTitle: Dropbox - 0313191128.jpg (at
emebaveraging on for smoother skirts - about 30dB down @ 100kHz offset17:37
emebcorrection - 200kHz offset17:39
MoeIcenowyif I have an oscilloscape I will try to do the experiment on UPduino2 and iCECream v117:46
tntiCECream ? didn't know that one.17:46
MoeIcenowyit's my own board ;-)17:49
MoeIcenowyonly 3 fully-installed ones exist on the world ;-)17:50
tntAh I see :)17:50
MoeIcenowyin fact it's available on my github17:50
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ylamarreThis whole project should just be renamed icepun or icywhatyoudid....18:26
* shapr snickers18:28
ylamarreYou shouldn't give this proposition the cold shoulder...18:28
ylamarreOr are you just having cold feet?18:28
shaprThe name symbioyosys got a laugh from me first time I saw it.18:28
ylamarreOk, symbioyosys is actually pretty good.18:29
soreardid you misspell symbiyosys or are you making a deeper joke I don't get18:30
ylamarreI followed shapr's spelling...18:31
shaprsorear: I got the spelling wrong, sorry18:32
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sxpertit's a nice pun on symbiosis, obviously19:49
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elmsLooking for some details on iCE40 IE/REN and ColBufCtrl. Is this the best place to ask (I know it's more icestorm than yosys)? If there is a document with more details I can start there.20:44
tpbTitle: Project IceStorm IO Tile Documentation (at
daveshahthis is indeed the usual channel for icestorm stuff BTW :)20:45
elmsdaveshah: I'd like to expand on that. Some IEREN control bits aren't in the ieren_db. why? Are they just never connected to package pins?20:46
daveshahYes, some possible locations are not bonded out in any package20:46
daveshahI have a suspicion that there isn't even a pad in some cases20:46
elmsok, but that's why they aren't in the table?20:47
daveshahIt wouldn't even be possible to fuzz them20:47
elmsdaveshah: For ColBuf are they there for lower power? If I understand, if they are all enabled, it will just draw more power.20:48
daveshahYes, it is perfectly safe to enable them all, always20:48
elmsdaveshah: as always thanks for bringing clarity.20:49
daveshahNo problem20:50
tntWasn't somebody supposed to decap and take UP5k dieshots ?  I saw some 'preview' on twitter but never the full detailled set.20:54
daveshahIt was Adam McCombs @nanographs20:57
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