Friday, 2019-03-08

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corecodei'll have to look into that00:00
corecodebut i do 4 layers anyhow00:00
emeb_macunless you use tricks like tinyfpga does where he allows pads to short together & lose I/O count00:00
corecodeuh no00:01
corecodeno hax00:01
corecodei think it should be fine00:02
corecodeif you break out diagonally00:03
emeb_macthey look like nice parts though - lots of resources.00:07
corecodeso maybe i'm wrong00:10
corecodebut 0.8mm ball pitch, that's 1.13mm diagonal00:11
corecodesay 0.3mm land diameter, so that's 831um between lands00:11
corecode0.2mm via drill + 120um anular ring = 391um left00:12
corecodewhich leaves 150um after 120um space00:12
corecodeso plenty room00:13
corecodei might be missing something00:13
cr1901_modern>to init BRAM from a file <--- $readmemh?00:30
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emeb_maccorecode: yeah - a few years back I did the math on putting vias & traces between pads on BGAs and it was still feasible for 0.8mm pitch02:20
emeb_maccr1901_modern: yes - that works for the complete build process starting from verilog. question was if it's possible to change BRAM contents *after* the bitstream has been built w/o redoing the whole synthesis/pnr/etc.02:22
emeb_macwould save some time for eg CPU code in BRAM ROMS02:23
cr1901_modernemeb_mac: Yes, use icebram for that02:26
cr1901_modernIt is statistically extremely likely to work02:26
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cr1901_moderneven though it relies on seeing a bitstream pattern that may or may not be valid outside of bram02:26
emeb_maccr1901_modern: yep - will give it a try02:29
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