Tuesday, 2019-03-05

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emebtnt: C compiler integrated into my repo -> https://github.com/emeb/icestick_650200:14
tpbTitle: GitHub - emeb/icestick_6502: A small 6502 system build on a Lattice Icestick FPGA development board (at github.com)00:14
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emeb_mac tnt: baby steps - got 6502 w/ cc65 working on a u4k06:31
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corecode\o/ u4k09:46
corecodei wonder how large that design is09:47
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tnt\o/ https://pastebin.com/mTs9MwN7   Ok, so it still has quite a few issues and the sw side is a huge hack but ...10:18
tpbTitle: [16389700.930124] usb 1-2: new full-speed USB device number 71 using xhci_hcd [ - Pastebin.com (at pastebin.com)10:18
corecodehi tnt10:22
corecodei'm debating implementing a HS USB SIE, so that i can skip the silly ftdi chips10:24
corecodebut maybe that's too much of NIH10:24
tntwell, for the ice40 I think this would take up way too much space to be relly useful.10:25
corecodealthough - you think HS would take much more space than FS?10:25
tntThere are some ARM with HS that really don't cost a lot more than they phy.10:26
corecodeyea the cheapest i found are the sam3u10:26
sorearHave you looked at valentyusb and the tinyfpga boards?10:27
tntcorecode: we were looking at nuc505dl13y  which is 2$10:28
tntsorear: what's your point ?10:29
corecodewho sells the nuc?10:30
soreartnt: tinyfpga did exactly what corecode is asking about -bitbang USB (forget which speed) on ice40 to avoid the footprint of a separate ftdi10:30
tntsorear: no, he's talking about HS ... 480mbps, you need a phy.10:30
tntcorecode: nuovoton directly.10:31
corecodegood, they had some availability issues10:31
corecodeuh wow that is a nice chip at that price10:32
corecodeah, embedded spi flash, interesting10:32
corecodethanks, that's a good lead10:33
corecodehow did you find them?10:33
tnthttps://github.com/icebreaker-fpga/icebreaker/issues/14 :)10:34
tpbTitle: Explore options for FTDI replacement · Issue #14 · icebreaker-fpga/icebreaker · GitHub (at github.com)10:34
corecodeah, samg as well10:37
corecodeah no10:37
corecodeclassic usb confusion10:37
corecodetnt: thanks, that's a great find10:48
corecodenow the question is, can it do a fast bidirectional bus10:49
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corecodei've used nuvoton chips some years ago10:50
corecodetook me a while to get the usb peripheral going back then10:50
corecodehm, doesn't look like there is any kind of bus mode10:53
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tntcorecode: SD Host is probably the best it can do.12:33
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corecodetnt: seems like a roundabout way to transmit data.  what do you think?14:31
tntcorecode: well it's not ideal, but that's probably the highest bandwidt peripheral on there.14:32
tntIt's basically a quad SPI port.14:32
corecodeand i guess DDR14:33
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shaprDoes this mean vmware/cascade would work better on a BeagleWire? https://github.com/vmware/cascade/issues/83#issuecomment-46938980717:26
tpbTitle: support for yosys backend? (or fill out "adding new backends" docs section?) · Issue #83 · vmware/cascade · GitHub (at github.com)17:26
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emebtnt: here's the 6502 project ported to a up5k -> https://github.com/emeb/up5k_650220:22
tpbTitle: GitHub - emeb/up5k_6502: A simple 6502 system built on a Lattice Ultra Plus 5k FPGA (at github.com)20:22
emebI tweaked it slightly to use one of the SPRAM cores for the main system memory, so the 6502 has 32kB RAM and 4kB ROM in this build.20:23
tntemeb: nice ! I'll try to give this a shot next week end :)20:25
tntemeb: what target board did you use btw ?20:25
emebtnt: I built it on a upduino I had laying around.20:26
emeband I used my custom-made USB->SPI board to directly load the up5k so you'll definitely need to tweak the "make prog" target for whatever programming hardware you have.20:27
tntI'll probably try on the icebreaker and use iceprog.20:28
emebtnt: great - I was hoping someone would try it on that. I don't have one so I can't do it myself.20:28
emebdoes icebreaker have a USB serial port hooked up to the FPGA?20:29
tntyes it does.20:33
tntthe same ftdi that's used for programming has a 2nd interface configured as uart.20:34
emebnice. so pretty much all you need to do is rearrange the pin assignments in the .pcf file to match the icebreaker I/O.20:34
emeband revise the 'prog' target in the makefile.20:34
tntI might try it tonigh. Depends how long it takes me to cleanup the microcode from my usb core :)20:39
emebcool - let me know if you run into any snags I could help with.20:58
tntIs there a demo app btw ? (didn't look really deep yet)21:06
tnthow is it loaded in spram ?21:06
emebThere is demo code but it's preloaded into a ROM that's implemented w/ EBR.21:25
corecodehow big is the cpu design?21:26
emebyou mean how much of the FPGA does the whole thing use?21:26
emebhere's the nextprn resource table: https://pastebin.com/eVVZnwnP21:28
tpbTitle: Info: Device utilisation: Info: ICESTORM_LC: 1043/ 5280 19% Info - Pastebin.com (at pastebin.com)21:28
emebplenty of logic left over21:31
corecodemakes me feel like my cpu design isn't too bad21:32
emebyours is smaller?21:32
corecodeyes, around 60021:32
corecodeand it is a 16 bit cpu21:32
tntcorecode: nice, that's about the size of my 16b cpu as well. Hard to go smaller.21:37
corecodeyea, the alu mux makes it quite big21:39
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emebhmmm... something weird going on with the ACIA. Works OK for TX but reading RX data isn't clearing the IRQ as it did in my other designs. grmbl.22:06
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emebfixed & pushed22:28
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