Monday, 2019-03-04

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esdentnt: has a photo of his bodge.00:00
cr1901_moderndo not underestimate my ability to screw this up00:00
esdenwhat you break you can fix ;)00:00
cr1901_modernhow do I lift just 3 legs off the chip?00:00
cr1901_modernesden: ENOEXACTO for broken traces00:01
esdenKevin Hubbard aka. Black Mesa Labs:
cr1901_modernOhhh right right00:01
cr1901_modernerr, ENOXACTO*00:01
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esdenHere we go... apropos:
sorearthere's a typo there right?02:01
soreartweet says "6800" but the chips on the board are marked "68020" and "68882" (discrete FPU, fanschy)02:02
sorearhas been discussed here, or anywhere else I ought to join?02:12
tpbTitle: [Eda-dev] 1st time silicon success on qflow! (at
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emeb_macso that opencores osdvu UART I used in my icestick 6502 demo has some very weird stuff going on in it.04:25
emeb_macin particular, the guts is all one synchronous process - blech.04:25
emeb_macand to top it off, they used blocking assignments for everything.04:26
emeb_macyosys mostly handled it OK, but there was one glitch where it crashed when I tried to use one of the outputs. I had to add some extra logic on the outside to make it work.04:27
emeb_macduring ABC step I'd get this: ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").04:34
emeb_macand then within a few more lines of the output log it would throw an exception and crash04:34
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emeb_mactnt: god help me - studying the cc65 docs to figure out how to make a custom target for this configuration. :P07:09
tntedit :)07:13
tpbTitle: cc65/Makefile at master · cc65/cc65 · GitHub (at
tntemeb_mac: I guess you just need driver for the serial ?07:15
emeb_mactnt: that, plus the linker scripts and startup code.07:16
emeb_macbut I've already written most of the serial I/O routines needed so it should go together pretty well.07:16
emeb_macthere's a tutorial in the cc65 docs that pretty much lays out what's needed for an FPGA-based 6502 that's similar to what I did.07:17
tntthat's nice of them :)07:18
emeb_mactnt: the makefile you linked has all kinds of cruft in it for existing 6502 systems (Commodore/Apple/Atari/etc) that's completely useless for this application. Would end up stripping 90% of that out.07:19
emeb_macusing the icestick limits the amount of ROM/RAM to just 8kB total and the system as-is uses about 80% of the fabric so this is nearing the limits.07:25
emeb_macmoving to a u4k or up5k will significantly increase the memory and periphs possible. SPRAM on the up5k opens things up significantly.07:26
emeb_macbut that'll wait until morning.07:26
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corecodewoh these ecp devboards are expensive12:41
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daveshahThe LFE5UM5G-85F-EVN isn't bad12:55
daveshah$99 for the biggest ECP5 and a year's diamond license12:56
ylamarreDefine expensive?12:56
corecodeoh you need a diamond license to use the ecp5?13:10
corecodethat's a downer13:10
daveshahYes, you need one to use any of the with SERDES variants13:11
daveshahThe non SERDES ECP5s don't need a license13:11
corecodecrazy that this is a business model they can do13:11
daveshahI think it's so they can give them for free to their big customers, to make those customers feel special13:12
srkthe rest of us needs to wait for RE efforts and opensource toolchain :D13:16
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somlodaveshah, what's the relationship between (which I can't actually access anymore) and PR #219 ?18:01
daveshahplacer_heap_ddrn was a rebase of placer_heap onto the ddr3 changes18:04
daveshahThe latter are now merged into master18:04
daveshahAnd placer_heap/#219 are on top of that (and should be used(18:04
keesjis the physical constraint file format documented somewhere?18:15
daveshahNo, it's a vaguely extended variant of the icecube format18:15
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somlodaveshah: I've been using #219 for a few weeks now, as it's awesomely fast compared to *not* using it -- works great for my use case (rocket-chip on ecp5), will try using it on the ddr3 litedram SoC today...18:50
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daveshahAwesome, I'm hoping to have it upstreamed fairly soon18:51
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keesjcan I add verilog files while in the yosys shell ? e.g. something like add but for verilog files19:27
keesje.g. something like
tpbTitle: Yosys Open SYnthesis Suite :: Command Reference :: add (at
keesjfound it (read_verilog) ..19:29
tpbTitle: Yosys Open SYnthesis Suite :: Command Reference :: read_verilog (at
corecodeERROR: Found error in internal cell $techmap\top.spi.$procdff$602 ($adff) at kernel/
corecodewhat could that mean?19:38
corecodewhat did i do wrong?19:38
daveshahThis was a recent regression, fix is merged I think.19:38
corecodeah thank you19:39
daveshahDoes your Yosys have
tpbTitle: Fix multiple issues in wreduce FF handling, fixes #835 by cliffordwolf · Pull Request #837 · YosysHQ/yosys · GitHub (at
corecodei'm building19:39
corecodeand i'll check with latest master19:40
daveshahLatest master should be fine19:40
corecodeyep that worked19:46
corecodehm, so now my simulation works, but doesn't seem to work on the fpga?19:53
tntcorecode: what are you trying to run ?19:53
corecodemy forth cpu19:57
tnton what board ?20:04
corecodemy own, u4k20:10
corecodemust be my mistake20:10
corecodepre-synthesis simulates right, post-synthesis does not20:10
corecodemy write strobe gets lost20:11
ylamarresim/synth mismatches are my favorites <320:12
ZipCPUylamarre: I wrote about that once some time ago ...20:14
ylamarreMost of the time they are uninitialized signals getting compared to 0.20:14
ZipCPUI tried to categorize as many sim/synth mismatches as I could get ahold of--thanks to the reddit folks20:15
ZipCPUUninitialized stuffs ... formal usually finds that for me, so that much is fairly simple20:15
ylamarreZipCPU: Hi, haven't had time to go through all your stuff, but from what i've looked there were some very good articles,20:16
tntpost-synthesis simulation is something I almost never do. Actally I rarely have something working in simulation and not in real hw.20:16
corecodewel this one doesn't :/20:17
ZipCPUThere's an icebox_vlog program that makes post-synthesis simulation very possible, even with Verilator.  Not sure it works with the u4k or not.20:17
tntdo you have an explicit reset line ?  (rather than relying on reg x = 1'b1) ?20:18
corecodeZipCPU: it does20:18
corecodei have a reset counter20:18
corecodeoh man, what a dumb mistake20:23
corecodealways @(posedge clk) if (reset) sig <= 0; else if (clk) sig <= somethingelse;20:23
corecodenot attentive, added a if(clk)20:23
corecodeunclear why this made it not synthesize "properly"20:24
corecodeand now it works!20:25
tntif rising_edge(clk) ... VHDL FTW !20:25
corecodenot sure how that would have helped20:25
tntcorecode: congrats :)20:25
tntThat's the 'gotcha' with verilog ... if you deviate from the best practice / templates ... you get crap synthesis results20:26
ylamarreWhere as with VHDL you'd get none?20:27
tntexactly. with vhdl it would throw an error :)20:27
tnt(or you just can't ... like there is no blocking / non-blocking stuff in vhdl so you can't get it wrong)20:28
ylamarreWell, there is variables vs signals, but, I guess those are not exactly the same...20:29
corecodebut shouldn't synthesis and simulation always agree?20:29
tntyeah, variables are local to the process.20:29
ylamarrecorecode: LOL20:29
corecodewell, if not, there must be a bug in the implementations20:30
ylamarreWell the uninitialized compare to 0 is a good example of both implementation being rigth, but still mismatching.20:30
tntcorecode: no ... verilog allows you to describe non-deterministic logic.20:30
tpbTitle: VHDL's crown jewel - Sigasi (at
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emebtnt: having some success w/ cc65 building ROM for the 6502 project. Kind of amazed it worked first time. :)22:47
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emebjust need to setup a recursive make for it.22:49
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tntemeb: Oh nice. Looking fwd to the up5k variant :p22:51
emebtnt: should be easy22:51
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