Sunday, 2019-03-03

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promach_corecode : spidergon routing algorithm will give deadlock, that is one bad thing about spidergon01:16
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promach_corecode : I mean for spidergon with all master nodes01:29
promach_ won't be able to help in this case01:29
tpbTitle: Turn restriction routing - Wikipedia (at
corecodecan you explain how it can deadlock?01:31
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emeb_machah, fun - got a simple little 6502-based system running in u4k (my breakout) and hx1k (icestick). fun part was setting up the makefile to include building the ROM contents from 6502 assembly code.01:38
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promach_corecode : spidergon with all master nodes will have the possibility of cyclic packet transaction01:46
promach_cyclic packet flow will lead to deadlock01:46
promach_this is all the fault with spidergon deterministic routing algorithm01:46
emeb_macgeneral question: when building a design in yosys/nextpnr, is there a way to just change the EBR contents w/o rebuilding everything from scratch?02:06
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corecodepromach_: why deadlock?09:07
promach_corecore : because packet went into cyclic path09:07
corecodea single packet?09:07
daveshahemeb_mac: there is icebram09:07
daveshahIt should work with vendor tools too09:08
promach_corecode : no, all nodes issue packet to the next neighbouring node09:08
promach_do you get it ?09:08
corecodewhy is that a deadlock09:08
promach_corecode : because deadlock is something that locks everything down09:08
promach_imagine all nodes send at the same time instant09:09
promach_with turn-restricion, then deadlock will not happen09:09
promach_corecode : but spidergon is using shortest path routing algorithm which does not consider the deadlock problem09:10
corecodecan you explain the deadlock09:10
corecodeyou're saying that it leads to deadlock, but i don't see how09:10
tntI think figuring out why 'xxx is "unused"' is where I spend most of my time when synthesizing stuff for the first time.09:11
corecodeso we start out by having all nodes send a packet to their neighbor09:11
promach_corecode : es09:11
promach_let say in a restaurant, we have a cicle of tables09:12
promach_and we have 8 tables09:12
corecodeno analogy09:12
promach_we have 8 couples09:12
corecodei can't work with analogies09:12
corecodemy brain can't translate09:12
promach_all of them are sitting in the table09:12
promach_all nodes are chained in a cicular manner09:12
promach_node 0 sends packet to node 109:13
promach_node 1 sends packet to node 209:13
promach_node 2 sends packet to node 309:13
promach_node 3 sends packet to node 409:13
promach_node 4 sends packet to node 509:13
promach_node 5 sends packet to node 609:13
promach_node 6 sends packet to node 709:13
promach_node 7 sends packet to node 009:13
promach_now do you see deadlock09:14
promach_moving packet across from one node to the another node requires time latency09:14
promach_this is physical world, remember09:14
promach_I mean hardware09:14
promach_wiring time09:14
corecodeso it takes, say, 32 clock cycles to transmit a packet09:14
promach_let say each packet transfer requires 1 clock cycle09:15
promach_node 0 cannot send packet to node 1 if node 1 does not have buffer space09:15
corecodewhy doesn't it have the buffer space?09:15
promach_node 1 cannot send packet to node 2 if node 2 does not have buffer space09:15
promach_because it is occupied09:16
promach_does not have enough buffer space09:16
corecodehow is it occupied09:16
promach_this has to do with all the packet routing09:16
corecodeplease explain09:17
promach_all nodes are initially full09:17
promach_because it is full09:17
corecodewhat's in there09:17
promach_filled from packets routed during previous timestep09:17
promach_do you get the meaning of deadlock now ?09:18
tpbTitle: Turn restriction routing - Wikipedia (at
corecodeit seems you're assuming that there is only one buffer for input and output09:18
tpbTitle: Deadlock - Wikipedia (at
corecodei know what a deadlock is09:19
promach_assume ?09:19
corecodeis this a question?09:20
promach_are you telling me that virtual channels will solve the deadlock issue ?09:20
promach_even in spidergon ?09:20
corecodeyou're not being rigorous09:20
promach_huh ?09:20
corecodeyou say "this is a deadlock", but you don't define any algorithm09:21
tpbTitle: Spidergon Networks-on-Chips : algorithms (at
corecodedo you actually look for feedback on what you're saying?09:22
corecodeor do you just want to be confirmed?09:22
promach_no, I am trying to find out ways to tackle deadlock problem in Spidergon09:22
corecodethen write an algorithm that will deadlock09:23
corecodeand then think about how to avoid it09:23
promach_already did09:23
promach_I mean the thinking part, not yet09:23
corecodeany cylic graph will have the problem you're describing09:23
corecodeso it's silly to say "oh no"09:24
promach_wait, probably virtual channels will help09:24
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corecodei think you're reading a lot and not doing a lot09:24
promach_no, reading helps09:24
corecodethinking helps even more09:25
corecodeif you can process your incoming data in one clock cycle, would you get a deadlock?09:25
promach_otherwise the code won't be correct09:25
corecodecode is never correct09:25
corecodebut it can approach correct09:25
corecodeit's an iterative process09:25
corecodeso it can't be a routing deadlock; if our processing in the node was just "receive packet and drop", it would work without problems09:26
corecodeso it has to be a processing issue09:26
promach_what processing were you referring ?09:27
corecodein the node09:27
promach_true, each node is a verilog module09:27
promach_and each verilog module has different latency09:27
corecodeif each node will just discard the incoming packet, it won't deadlock09:27
corecodeso it is not a problem of the network09:28
promach_but we have tackle this problem through network concepts09:28
promach_using virtual channels will solve the deadlock issue09:28
corecodei'm done with you09:28
promach_but I am not sure09:29
corecodei think you're a robot09:29
corecodeoff in ignore you go09:29
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corecodesorear: me?09:45
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keesjdaveshah: great work on ECP5 DDR3!
corecodeoh i should get into the ecp511:06
daveshahthanks keesj!#11:12
corecodeyeah, cool11:14
corecodeoh no, the q&a of your fodem talk was cut short11:16
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corecodedaveshah: is there a list of what dies exist for the ecp5?11:31
daveshahIt's 25k, 45k, and 85k11:31
daveshahthe 12k is a rebadged 25k11:31
corecodedo they all have serdes?11:31
daveshahProbably, but it's the most likely thing to have yield issues11:32
daveshahso I wouldn't bank on it being in-spec on non-serdes parts11:32
corecodei see11:32
corecodebut good enough to play with11:32
daveshahhaven't ever tried it11:32
daveshahdon't have any boards around with a non-serdes ecp5 that exposes the necessary pins11:33
corecodebecause the UM (serdes) parts seem to be 3x the price11:33
tntWhat I'm wondering is if the 5g part could run at 6.144G ...11:38
corecodewhere is that rate used?11:39
daveshahGiven that the 5G parts are already 'over-volted' my suspicion is they are quite marginal11:39
daveshahwouldn't be too surprised if some could run at 6.144G though11:40
tntcorecode: with 2x6.144G you can get a 10G ethernet lane.11:40
corecodeah, the 256-CABGA is 0.8mm pitch11:40
corecodethat's at least possible in fairly low price process11:41
somlodaveshah: also want to say congrats (and thanks) for the ecp5 ddr3 thing!12:21
somlois it in litex proper, or in a fork or PR?12:22
daveshahThe DDR3 stuff is now upstream12:23
daveshahThe SoC with Ethernet is here:
tpbTitle: GitHub - enjoy-digital/versa_ecp5: Versa ECP5 SoC based on LiteX (at
somloso litedram proper and versa_ecp5, then -- cool!12:23
somloI need a starting point to rip out just the dram controller and the C program used to initialize it, so I can graft it onto the rocket chip based SoC :)12:24
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somloso Lattice have decided to send me a proper 5g versa board, and they're letting me keep the franken-version with a non-5g FPGA -- might be worth something as a weird collectible one day in the future (or not) :)12:31
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MoeIcenowysomlo: board with wrong chip?15:28
MoeIcenowycollectible ;-)15:28
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MoeIcenowydaveshah: btw is DFF initialization implemented in ECP5 Yosys?19:13
daveshahMoeIcenowy: yes, it is now19:13
tpbTitle: yosys/ at master · YosysHQ/yosys · GitHub (at
MoeIcenowydaveshah: in fact I think I have done the same thing for Anlogic19:14
MoeIcenowyvia "dffinit -strinit SET RESET -ff AL_MAP_SEQ q REGSET -noreinit"19:14
MoeIcenowydo you think this scheme familiar? ;-)19:15
daveshahyeah, this pass also has to deal with conflicts between sync set/reset and initialisation (by blowing the sync set/reset back to logic in a conflict)19:16
MoeIcenowyoh maybe I should drop my code and port ecp5_ffinit to anlogic19:17
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emeb_macstupid 6502 + UART running on an icestick. just because ->
tpbTitle: GitHub - emeb/icestick_6502: A small 6502 system build on a Lattice Icestick FPGA development board (at
cr1901_modernahhh you used Arlet's core nice21:56
tntemeb_mac: now you need to pport basic to it :)21:56
cr1901_modernoh cool, you made an acia too21:58
cr1901_modernnext is via and pia ports :P?21:58
emeb_mactnt: rofl21:58
emeb_mactnt: I actually have BASIC running on the one I did for up5k21:59
emeb_macbut it's too big to fit into the BRAM on the hx1k21:59
tntoh you have a up5k version somewhere ?21:59
daveshahRun on SPI flash?21:59
emeb_mactnt: yeah - haven't published it though - not quite done yet21:59
daveshahOr implement virtual memory and load pages from the UART :P21:59
emeb_macdaveshah: heh22:00
emeb_maccr1901_modern: the acia is just a wrapper around a simple UART core I found on github22:00
emeb_maccr1901_modern: and on closer inspection that UART has some issues. But it's good enough for a demo. :)22:01
cr1901_modernand 65816 has virtual memory support; I don't think 6502 does22:01
emeb_maccr1901_modern: no - it's just straight 64k w/o banks, mmu, etc22:01
cr1901_modernthere's an old 74xx chip that is called an "MMU", but it's more accurately called a bank switcher22:02
sorear65816 has bank registers but no protection/remapping?22:23
cr1901_modern65816 has an abort pin that restarts the current insn22:24
cr1901_modernthis means in principle you can add memory protection/remapping22:24
cr1901_modernBut I've seen the abort pin used exactly once22:26
cr1901_modernin someone's custom computer22:26
cr1901_modern(Back in 2015 I asked for the source code- it was made using one of Lattice's GUIs a la icestuido22:26
cr1901_modernI still have it somewhere, but never got around to studying it22:27
tpbTitle: ASICMMU (at
cr1901_modernNote that adapting this to modern FPGAs... well, it stinks. 65816 is a 5V CMOS CPU, so TTL levels don't work for it and associated peripherals22:44
cr1901_modernon the other end of the MMU you'll need level shifters for 5V CMOS peripherals that natively speak to 6581622:44
emeb_macI've been lurking over on that Commander 16 project on FB where they're trying to design a 65816 retrocomputer.22:46
emeb_macit's kind of hilarious/sad all the conflict they're having over the use of FPGAs22:47
cr1901_modernwell, maybe you don't need all that much converted back to 5V on the I/O side of the MMU... a greenpak powered at 5V could do dual addr decoding and level shifting22:49
tntemeb_mac: is that the 8bit guy project ?22:54
cr1901_modernHe rubs me the wrong way22:54
cr1901_modernbut I could just be jealous of his success22:54
cr1901_modern(and there are some... flaws w/ his "how 8-bit graphics work" that my NES hacker friends like to point out :P)22:55
cr1901_modern"how 8-bit graphics work" video*22:55
tntoh yeah, it's not always the most technically accurate. For that gotta watch the 'ultimate talks' series from ccc :p22:56
tntwe need a 'ultimate ice40 talk' with all the tech details of all the blocks the routing and all that stuff :)22:57
emeb_mactnt: yes22:57
emeb_macit's a neat idea, but their self-imposed limits seem kind of shortsighted, and I suspect they'll have a hard time hitting that $50 price point goal without losing their shirts.22:59
tntI didn't read anything on the fb group, but esden and I actually sent him a proposal for an ice40 gpu (and matching hdmi driver and bus interface), but he turned it down, so didn't really follow after that.23:01
cr1901_modernc256 foenix looks interesting23:02
cr1901_modernit's sorta what I would do if I were making my own 65816 computer23:02
cr1901_modernI would use FPGAs for: address decoding, MMU, i2c bus, uart, and spi bus. The UART is because the current ACIA silicon by WDC is very broken23:03
esdenI had a few back and forth with him when he turned us down. Regarding pricing. He insisted it was fine to use the xilinx chip for video, because someoen told him he will be able to source the chips for $5. I ended up wishing him good luck, and if he is interested he knows how to reach us. :)23:03
esdenAnd honestly. I am even more curious if he will be able to source the 65C2xxx chip for a reasonable price. Without good chip distributor contacts and large production quantities, these things are not that simple to get.23:05
cr1901_modern65c2xx is the microcontroller variant IIRC23:06
cr1901_modernit's an interesting beast23:06
esdenI don't doubt it is interesting. ;)23:07
cr1901_modernesden: I like WDC a lot- they are receptive to hobbyists inquiries. But it's quite a mystery to me where their actual business comes from.23:07
cr1901_modernb/c it ain't from Joe nobody like me23:07
daveshahPlenty of still built old designs I'm sure23:08
daveshahParticularly applications which are certified and expensive to change23:08
cr1901_modern(the VP of Business and Development David Cramer helped me out personally over email when I had trouble buying some 65816s a few years ago from a vendor.)23:08
cr1901_modernWDC is fabless; they used Sanyo up until I want to say 2015; now they use TSMC23:10
esdenYeah the amount of old chips in industrial applications is astonishing. I bet in certified systems there is even more of that.23:11
cr1901_modern(Tbh, I thought for the longest time Sanyo was a kitchen appliance manufacturer)23:11
emeb_macWDC is about 5 miles from where I live.23:12
cr1901_modernOh that's cool23:12
cr1901_modern>In 2010, Sanyo sold its semiconductor operations to ON Semiconductor. [16] Oops23:12
sorearAre they still using the old masks for anything or is the Verilog version the only one now23:13
emeb_macbut I agree with esden that they'll have trouble with pricing, not just on the CPU & FPGA too.23:13
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sorearMy general philosophy on this sort of system stuff is you want to balance complexity between components, and using a ca. 10 kGE core like 65816 with >>1Mbit of memory is unbalanced and silly23:15
emeb_macheh - the village idiot driving a lamborghini :)23:17
esdenI also heard him say, "I am not concerned about the hardware that much, software is much more important at the moment." although I partly agree. He did mention the aggressive $60 retail target, and I think they are being overly optimistic. To emeb_mac's point, even if the main components seem to be "gettable" in the right price bracket, there is a lot of supporting components that will add up.23:17
cr1901_modernsorear: I dunno... in principle 65816 could run a full fledged *nix if you actually gave it a full 16MB of RAM. The main problem is that functions have to be limited to 64kB boundaries (or a linker relaxation pass would have to break a function that straddled the boundary into two chunks).23:18
sorearwho are we talking about?23:18
cr1901_modernI think that would be cool23:18
cr1901_modernsorear: 8-bit guy23:18
soreari,i Sanrio semiconductors23:18
emeb_macThose Spartan 6 LX9 chips are listed @ ~$18 / qty180. You might be able to get them cheaper if you cozy up to the Xilinx reps and get the "friend & family" pricing. This project *might* be high enough profile that they'd buy in. Might.23:20
daveshahUnlikely, with my experience of Xilinx reps in the UK a few years ago at least23:22
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daveshahThe best price we got was higher per unit than digikey23:22
daveshahIn qty 100023:22
emeb_macA guy I know managed to talk Xilinx down to about $10 for an SDR project he was going to do, but there were a lot of strings attached.23:23
emeb_mac(on the S6 LX9)23:23
daveshahI suspect in this case they are relying on cheapo "secondary" distributors23:24
daveshah Not a risk I'd take for something like this, but each to their own23:24
emeb_macever popular Chinese gray market23:24
emeb_macice40 HX would definitely be a better bet for something that doesn't need lots of DSP cores.23:25
esdenYeah, I can confirm that it really depends on how cozy you are with the "right people" from the chip vendor. And developing those relationships takes a lot of time, even if you have a "high profile" project. But who knows he might know someone, he does have a lot of tech people watching his channel.23:26
cr1901_modernI really can't watch many retro channels on YT. I just get sad that I either A. missed my chance to get a piece of the retro pie, and/or B. don't have the right personality to have pulled off being a popular retro enthusiast lol23:28
cr1901_modernThat market is very well saturated now23:28
esdenI try to tell myself that I do not have space or time for it anyways. So I enjoy the fruits of the other people’s labor here. I have enough things to play with... ;) but sometimes I have similar feelings cr1901_modern23:32
cr1901_modernesden: The first step towards fixing a problem is admitting it exists. Well, I'm not really about the fix these jealous feelings tho LOL23:34
cr1901_modernIf someone wants to dunk on 8-bit guy, and I know their credentials, I'm prob gonna listen. And wish it was me doing said videos and sipho- err making money off ppl's nostalgia instead23:35
cr1901_modernI mean shit, of course I'd love to be able to talk about/make hardware for obsolete machines and not have to worry about other work XD23:36
daveshahGet a job in the railway industry then :P23:36
daveshahOr military or marine23:37
esdenOr aircraft...23:37
cr1901_modernHmmm, well I do like trains (although foamers ensure I'll never talk about that out loud)23:37
esdenMy PnP is the biggest retro project that I have... and I would prefer if it was not retro to be fair... on the other hand it is probably easier to maintain without a support contract. ;D23:38
esdenPick and Place machine23:38
cr1901_modernYou're making an ISA Plug-n-Pray FPGA core?23:38
cr1901_modernyea I don't have the spare money for that23:38
esdenwell... it is not a toy in my case. I wish it was just that.23:38
esdenAhh the utopia where one can just work on interesting shit without worrying about materialism. :/23:40
cr1901_modernHmmm fair point. I wasn't thinking of using it as a toy, but to make prototyping during contracts easier23:42
cr1901_modernsince I'm not a wonderful manual pick-n-place machine23:43
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cr1901_modernesden: Was the 3-bit HDMI icebreaker PMOD meant to be a prototype?23:55
cr1901_moderncontrast to the 16-pin PMOD23:55
cr1901_modernor was there supposed to be an 8-pin 3-bit and 16-pin "whatever"-bit verson?23:55
esdenFor less boards than 10 it is usually faster to place by hand than setup a PnP.23:57
esdenThe 3bit one was a prototype based on Kevin's design. The 4bit version is the successor to it, based on tnt's suggestion. This is what I will be making and selling in the store. The 12bit version is part of the crowd funding campaign, and this is what "people" will be getting.23:58
cr1901_modern(who is Kevin, btw?)23:59
cr1901_modernanyways I have the 3-bit version which is fine for my needs. Making the 4-bit at home might be fun23:59
esdenThere is a new version of the 4 and 12 bit coming, with more jumpers, again a good suggestion from tnt. ;)23:59

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