Saturday, 2019-03-02

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promach_corecode : do you think yosys-smtbmc is able to do NoC deadlock verification ?03:26
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shorneHello, I am trying to synthesize mor1kx (an openrisc core) with yosys.  I'm using the today's git version of yosys for the first time08:24
shornejust trying to run something like : yosys -f verilog -o synth.v -S mor1kx_dmmu.v mor1kx_true_dpram_sclk.v mor1kx_immu.v ....08:26
shorneafter MEMEMORY_MAP phase I just get "Killed"08:27
shorneand it exits08:27
shornesomething I am doing wrong?08:27
tntDoes 'dmesg' say anything ?08:30
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daveshahshorne: is it possible there are any large (e.g. tens to hundreds of MB) RAMs in there?09:29
tntI would more suspect a RAM that ends up not being mapped to ... RAM.09:35
daveshahNo RAMs will be mapped to RAM with -S which is generic logic synthesis09:37
shorneok, maybe I am missing ram mapping09:37
shornethere might be around 1 MB or ram09:38
shorneWe have caches and a ton of registers09:39
shornebut not that much09:39
shorneRunning again09:39
shornetnt: right its the oom killer09:39
shorneOut of memory: Kill process 21146 (yosys) score 614 or sacrifice child09:39
tnt1 MB done in FF is ... a lot of FF and muxes and ... :p09:40
shorneok, it worked after doing:  yosys -f verilog -o synth.v -p memory -p opt -S mor1kx_dmmu.v  ...09:43
shorneI was thinking the MEMORY_MAP was doing the memory conversions09:43
shorneSorry, first time using yosys09:43
shornerecently I have just been using iverilog/verilator ... not synthesizing anything :)09:44
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corecodepromach: how would you detect a deadlock?11:24
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corecodepromach: what did you implement for your NoC so far?11:43
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develonepi3andrewrk, updated zig ver c4887d7f. This is the cmd that I used to get zigmain.o zig build-obj -isystem ../../include/ -isystem /usr/lib/arm-none-eabi/include -isystem /usr/lib/arm-none-eabi -target armv7-freestanding-gnueabihf zigmain.zig.13:28
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promach_corecode : if I use Spidergon, then I am afraid that I cannot avoid deadlock.  I am not sure if I could combine Spidergon with turn-restriction routing14:50
promach_I am not sure if I even want to detect14:51
promach_when I could avoid/eliminate deadlock entirely14:51
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corecodewhy would you get a deadlock?15:48
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FL4SHKDoes yosys have a VHDL frontend?18:48
FL4SHKalso, regarding formal verification with yosys, is there any way to do so with VHDL?18:49
FL4SHKMy guess and possibly correct "knowledge" is that neither of these are available.18:50
FL4SHKI thought I'd ask anyway, though.18:50
tntThere is a commercial 'plugin' I think.18:51
daveshahFL4SHK: There are some experimental projects to add VHDL frontends to Yosys, ime the best option is vhdl2vl18:51
daveshahThe commercial frontend is Verific. This does support formal verification, at least asserts (not sure about assumes)18:51
daveshahIf your purposes are research/personal/academic a free license might be available18:52
daveshahsee and
tpbTitle: Research Partner License Program (SERP) Symbiotic EDA (at
FL4SHKvhd2vl's existence actually surprises me18:52
FL4SHKdoesn't support pcakages, structures, or functions?18:54
FL4SHKwithout those features, I have no need to use VHDL18:54
daveshahNo, vhdl2vl pretty much supports the verilog feature set only18:54
FL4SHKguess I'll continue with my compiler project then, heh.18:55
FL4SHKI'm not working on a VHDL compiler, but rather a compiler for a custom HDL18:55
FL4SHKit'll be spitting out Verilog-200118:55
FL4SHKthe fact that it carries over comments is intriguing18:56
FL4SHK*the fact that vhd2vl18:56
FL4SHKI may or may not want to do so myself...18:57
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