Friday, 2019-03-01

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promachcorecode : the problem with NoC compared to regular bus is that we might have some problem determining the starting packets nodes as well as finishing packets nodes09:06
promachin other words, for a task to be loaded into the computation units within the NoC, it is a bit difficult to determine the start nodes and finish nodes09:07
promachso, it is more about finding out where the data entrance and exit points09:08
promachcorecode : have you done some coding on NoC previously ?09:37
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promachit is really a headache to do the mapping of computation task to the computation units within a NoC09:54
promachI mean without the help of gcc compiler10:01
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corecodehi promach12:10
corecodewhy is it hard?12:11
corecodewhat computation do you want to do?12:11
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* sxpert is having fun with logisim-evolution12:34
sxpertfinds it more intuitive than bare verilog12:35
corecodewhy intuitive?12:37
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promach_corecode : see figure 2 of
tpbTitle: Sci-Hub: устраняя преграды на пути распространения знаний (at
corecodethis is all academic research wank13:35
corecodeyou need to use more words13:35
promach_I am trying to map some different computation DFGs to NoC13:36
promach_remember I have few DFGs to work with13:36
corecodei don't remember13:36
corecodebecause i never was shown13:36
promach_corecode : so basically, I have few computation maths equations to be calculated using multiple processing units within the NoC13:37
promach_DFG means data flow graph13:37
promach_something that is formed from maths expressions, do you get it ?13:37
corecodeyes, i know what a dfg is13:38
promach_like how the data from intermediate operations are led to the next operation13:38
promach_and how the final result is obtaied after multiple path traversal13:38
promach_now, I have some DFGs13:38
promach_and to be mapped onto the processing units within the NoC13:39
MoeIcenowydaveshah: could I ignore RGB driver and assign general SB_IO to RGB pins of UP5K?13:40
MoeIcenowyok good13:40
daveshahbut they are always open drain13:40
daveshahno pullup either13:40
MoeIcenowydaveshah: no problem, I connected them to the negative side of LED13:40
MoeIcenowy(but I didn't connect resistors...13:41
MoeIcenowy(refered the design of UPduino13:41
promach_corecode : do you now understand what I am trying to do with the DFG ?13:45
corecodebut what do you want to do concretely13:46
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promach_corecode: mapping DFG to NoC14:32
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MoeIcenowyoh I changed my design to use PLL out as clock15:06
MoeIcenowyand then the full design got optimized out by Yosys15:07
MoeIcenowyoh dropped the judge of locked at internal reset generation15:07
MoeIcenowysorry for false positive15:07
MoeIcenowyI used wrong name for locked signal when defining SB_PLL40_CORE15:08
MoeIcenowydaveshah: what's corresponding timing config in iCECube2 is used for icetime?15:21
MoeIcenowyand when running icetime with a design that uses all clocks derived from PLL15:22
MoeIcenowywill icetime output the freq requirment of PLL out or PLL in?15:22
MoeIcenowy(I assume PLL out15:22
daveshahneither, icetime supports a single constraint on all clocks15:23
daveshahpassed by command line15:23
MoeIcenowyoh so in my situation it's PLL out?15:23
MoeIcenowy(because in all alwayses pllout is used15:23
corecodepromach_: which DFG15:24
MoeIcenowydaveshah: for UP5K, is icetime using commercial temperature range or industrial?15:25
tpbTitle: icestorm/ at master · cliffordwolf/icestorm · GitHub (at
daveshah85 degrees, 1.14V, worst15:26
daveshahsame as icecube defaults afaik15:26
MoeIcenowyI'm now thinking soldering a 50MHz osc on an iCE40UP5K board may be too high?15:27
MoeIcenowyon my design with Altera Cyclone IV and Anlogic Eagle-4 (both uses proprietary toolchian) that can reach 100MHz+15:28
daveshahCan always divide it down15:28
MoeIcenowyiCE40UP5K gets only 40Mhz+15:28
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daveshah50MHz is towards the upper limit of what the up5k can do15:28
MoeIcenowyI start to doubt whether iCECube2 or Radient can do 50MHz+15:29
tntWell ... depends what you're trying to do ... but icecube2 can definitely do stuff that runs above 50M.15:37
tntBut if you're trying to make a 20 layer combinatorial logic block, that's clearly not going to fly ...15:37
MoeIcenowyoh icecube2 refused my design with icestorm15:40
MoeIcenowyjust error with no message when "Import P&R Input Files"15:40
tntyeah you can't mix toolchains.15:40
tntin/out are not compatible.15:40
MoeIcenowytnt: I used no SB_ cells for IO15:41
MoeIcenowyI only used SB_RGBA_DRV and SB_PLL40_CORE15:41
tntI meant you can't feed a yosys output into icecube.15:41
MoeIcenowyI didn't feed the yosys output15:42
MoeIcenowyI feed v's to Synplify15:42
MoeIcenowySynplify succeed15:42
tntOh ok, sorry I misunderstood.15:43
tntCan you paste your code ?15:44
tpbTitle: GitHub - Icenowy/bfcpu: A simple CPU that runs Br**nf*ck code. (at
MoeIcenowyiCECube2 proj not included15:44
MoeIcenowyjust add verilog sources specified in Makefile_icecream_v1 and icecream_v1.pcf to proj15:44
promach_corecode : is one example15:45
tpbTitle: Ubuntu Pastebin (at
promach_this is sort of manipulating how the final result is obtained15:46
promach_corecode : from the c code, get a DFG (this is usually done by compiler tool, not human)15:46
promach_and the DFG is optimized by human for hardware15:47
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corecodewell, good luck15:49
tntMoeIcenowy: Import "P&R" file works fine here.15:50
tntPlaced and routed as well.15:51
daveshahfyi, just tried your design and noticed the critical path is posedge->negedge which icetime doesn't handle correctly15:52
daveshahnextpnr does, and gives 25MHz Fmax15:52
MoeIcenowynextpnr can deliver timing info?15:55
MoeIcenowytnt: maybe my iCECube2 is cursed?15:55
daveshahyeah, it has much better timing analysis than icetime15:55
daveshahalso supports multiple clocks unlike icetime15:55
MoeIcenowyI used 2017.0815:55
tntMe too15:55
tntyou might want to retry to create a project from scratch. I kno corecode (IIRC) also has issue witha  corrupted project file / env throwing stuff off.15:56
MoeIcenowyI just created it...15:56
corecodeyep, i don't know what i did, but it failed to place15:56
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MoeIcenowyI will try Radiant then15:57
MoeIcenowytnt: did you import the PCF?15:57
tntI did15:57
tntRadiant is annoying because they changes the primitives, so you can't have same code with instanciated primites that works in icecube and in radiant.15:57
MoeIcenowy"/home/icenowy/git-repos/bfcpu/i_mem_icecream_v1.v":16:1:16:9|Cannot find data file instructions_icecream_v1.hex for task $readmemh15:59
MoeIcenowyWTF? Synplify Pro cannot find the hex file in the same directory with source file?15:59
MoeIcenowytnt: where's the Radient primitives library?16:01
MoeIcenowyBTW I recreated a proj, and still failed to PnR16:01
corecodeno, it cannot16:01
corecodethe synplify project is elsewhere16:01
MoeIcenowymaybe it's now the time for `rm -rf ~/fpga/lattice/iCEcube2.2017.08/`?16:01
MoeIcenowyremembered when attending our "Laboratory of Computer Organization" lesson, the teacher warned us that under Vivado only absolute path will work for $readmemh16:05
tntWell to be fair yosys also looks for file in cwd and not in the same directory as the source file. I wish verilog had the same as C for include where using "" searches the same dir as the source.16:13
daveshahheh, looks like we actually beat icecube in this case16:14
daveshahicecube is reporting 22-24MHz across runs, nextpnr with the new criticality driven placer is getting 25-27MHz16:14
tntdaveshah: ? I get 36.98 MHz with icecube16:14
daveshahis it picking up the hex file?16:15
tntOh ...16:15
daveshahI was getting around that when it wasn't processing the readmemh and optimised half the core away16:15
MoeIcenowyseems that if hex is not picked16:15
MoeIcenowythe whole i_mem is optimized out16:15
MoeIcenowytoo clever16:15
daveshahsynthesis tools are too clever until they aren't clever enough :P16:16
MoeIcenowydaveshah: it's still not clever enough to optimize the whole core ;-)16:16
MoeIcenowyoptimize it to fixed 000 output ;-)16:16
daveshahat some point you hit the halting problem16:16
MoeIcenowydaveshah: BTW how to let nextpnr generate timing report?16:17
daveshahit does it automatically16:17
daveshahjust look towards the end of the output16:17
daveshahunless you run with -q, then it will only print failures16:17
MoeIcenowydaveshah: by proving it's not a turing machine halting problem can be solved16:17
daveshahyes, this is true16:18
tntdaveshah: indeed, now I get 23.5M16:19
MoeIcenowyI think maybe if we try to inject not-so-optimized yosys result to iCECube2 PnR16:20
MoeIcenowyit will be lower freq16:20
daveshahyeah, Yosys does struggle a bit with some optimisations atm16:21
tntIs there a way to feed synopsys output to nextpnr ?16:21
daveshahnot sure if it can export anything other than an edif16:22
MoeIcenowydaveshah: it says to export VQM16:22
daveshahthat might work16:22
MoeIcenowybut I don't know whether Lattice ver of Synplify supports it16:22
MoeIcenowyoh maybe it's now the time for me to rebuilt nextpnr16:23
MoeIcenowymy nextpnr version here only produces 22MHz16:23
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MoeIcenowyand fails timing check16:23
daveshahI'm on my working branch which is this PR:
tpbTitle: HeAP-based analytical placer by daveshah1 · Pull Request #219 · YosysHQ/nextpnr · GitHub (at
daveshahthis both improves the current placer1 and adds a new placer16:24
daveshahI was actually using the improved placer1 to get the 27MHz result16:24
daveshahhoping this gets approved and merged this week16:24
MoeIcenowyso a rebuild is really useful?16:25
daveshahI don't think rebuilding master will make much difference16:25
MoeIcenowyBTW does rebuilding master require rebuild icestorm?16:25
daveshahyes, because the u4k device was added16:25
MoeIcenowydaveshah: how does --opt-timing work?16:27
daveshahthat runs an extra post-placement pass that can improve timing a bit (at the expense of runtime, and not always improving)16:27
daveshahmaster with opt-timing gets me 27.9Mhz16:28
MoeIcenowyhears so good16:28
MoeIcenowyso maybe master will help16:28
MoeIcenowycurrently mine is 19cffde16:29
tntdaveshah: synopsis can actually write out a mapped verilog netlist.16:29
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MoeIcenowytnt: it's VQM16:29
MoeIcenowyoh that reminds me of the VQM generated by Yosys not recognized by Quartus Prime 18.116:30
daveshahyeah, just found it16:30
MoeIcenowyVQM seems to be a quite strict Verilog subset16:30
MoeIcenowyBTW something interesting: AGM Supra, which uses Quartus II defaultly as its synthesis suite, can read Yosys VQM (because Yosys is also its choice)16:31
daveshahLooks like it needs a definition of SB_RAM512x8NR16:32
daveshahthen Yosys should handle it16:32
tntFor some IPs the config seem to be attributes rather than params, that ight be anissue.16:32
MoeIcenowynow I start to believe iCE40 has really bad timing16:34
tntThe UP5K is optimized for ultra low power, not for speed.16:39
daveshahso looks like nextpnr gets 22MHz on the synplify netlist16:39
MoeIcenowytnt: HX is for speed?16:39
tntMoeIcenowy: yes.16:39
MoeIcenowydaveshah: the same branch with Yosys netlist?16:39
tntalthough ... it's still a 'low power class' so don't go expects Xilinx 7 series level of perf.16:39
daveshahMoeIcenowy: 27MHz16:40
tntdaveshah: interesting.16:40
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MoeIcenowyreally interesting16:40
MoeIcenowyhow about LC usage?16:40
MoeIcenowyBTW is there anyone crazy enough to attach a SDRAM to iCE40UP?16:41
daveshahSynplify wins, about 455 LCs compared to 50316:41
MoeIcenowytnt: I used to expect Cyclone IV E level of perf16:41
tntI have 0 experience with altera so ... can't comment.16:42
MoeIcenowymy main experience is with altera16:42
MoeIcenowythen anlogic16:42
MoeIcenowythen xilinx16:42
MoeIcenowysilliconblue just started16:43
MoeIcenowyand never any experience with genuine lattice16:43
MoeIcenowydaveshah: I remember synplify always win on space to yosys16:44
MoeIcenowyit might be useful if you want to use LP384 ;-)16:45
daveshahyeah, seems to win on space but not timing (tried setting a timing constraint but didn't seem to change things)16:45
MoeIcenowyBTW for FPGA REing I now think the infomation given by vendor toolchain is very necessary ;-)16:46
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MoeIcenowyI abandoned to RE AGM AG1280 because it can give out no useful info except a JTAG sequence used to burn the FPGA16:47
MoeIcenowyLattice and SiliconBlue toolchain seem to deliver many useful internal info16:48
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corecodeyou mean it doesn't produce a binary?17:05
MoeIcenowycorecode: it do produce, but a binary cannot be burned at all17:06
MoeIcenowyto burn the bitstream into SRAM the JTAG sequence is needed17:06
MoeIcenowyand binary cannot be furtherly converted17:06
MoeIcenowythe only chance of generating JTAG sequence is when PnR17:06
corecodeso what is the holdup for RE?17:07
MoeIcenowyyou cannot even judge whether the binary file is meaningful17:09
MoeIcenowyI remember at least one generation function of AGM Supra generates useless output, that is what the FAE says17:09
corecodeyou mean whether the vendor tool produced a correct bitstream?17:09
corecodewell that is a requirement of course17:10
corecodeor you would have to verify the behavior from the outside17:10
MoeIcenowybut the bitstream file is not used in any process at all17:10
MoeIcenowyonly the programming command file is useful17:11
corecodejtag command sequence is the equivalent to a bitstream17:11
MoeIcenowybut I think extract info from it will be weird17:11
corecodenot different from a bitstream17:11
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MoeIcenowyoh for the previous PnR failure on iCEcube217:30
MoeIcenowyI just checked my dmesg17:30
tntOOM ?17:31
MoeIcenowyit says "edifparser[15356]: segfault at 0 ip 00000000f7e9d5e2 sp 00000000ff905838 error 4 in[f7e92000+11000]"17:31
MoeIcenowyjust segfault17:31
MoeIcenowyno OOM17:31
tntah well.17:31
MoeIcenowynot only edifparser can fail on Yosys EDIF, but it can also fail on Synplify Pro EDIF17:32
MoeIcenowynextpnr perfectly outperform iCEcube2 here by no segfault17:33
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