Wednesday, 2019-02-27

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emeb_macup5k w/ USB for futzing w/ TinyFPGA USB bootloader sent to OSHpark03:01
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promachcorecode : so, I guess it is a better idea to stop the sby ?04:12
promachstill had not finished yet :(04:12
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MoeIcenowyemeb_mac: for the TinyFPGA USB BL, is any IO suitable for USB or a differiental pair specified by the pinout table is needed?10:39
daveshahAny IO works10:39
daveshahyou can't use a FPGA diff receiver on its own for USB <3.0 in any case, as it has some single ended signalling modes10:40
promachcan't use a FPGA diff receiver on its own for USB 2.0 ?10:43
promachdaveshah : why ?10:43
daveshahpromach: because USB has some single ended modes (where both pairs are at the same value)10:44
tntCan yosys infer dual clock RAM with different read/write width ?10:44
daveshahtnt: yes, hopefully10:44
promachI see10:45
daveshah*both lines of the pair, not both pairs10:45
tntdaveshah: I tried this, but ...
tpbTitle: module usb_ep_buf #( parameter TARGET = "ICE40", parameter integer RWI - (at
promachdaveshah: but wait, what about tinyFPGA BX ?10:45
daveshahpromach: that is USB 1.110:45
daveshahand uses just two single ended pins10:46
promachwhat about the upcoming EX version ?10:46
daveshahUSB 1.1 doesn't need any kind of diff receiver10:46
tntwell technically you can have a 2.0 compliant device that does FS only ...10:46
daveshahthat supports 1.1 on IO pins or 3.0 on the transceivers but not 2.010:46
promachso, is USB 1.1 , and not USB 2.0 ?10:47
tpbTitle: GitHub - davidthings/tinyfpga_bx_usbserial: USB Serial on the TinyFPGA BX (at
tntpromach: It's usb full-speed.10:47
promachso, it is USB 2.010:47
tntIt's USB 2.0 compliant (well ... maybe, didn't check if they passed the compliance tests), but it doesn't use the 'High-Speed' mode that was introduced in USB 2.0.10:48
tntLS = Low Speed = 1.5Mbps  FS = Full Speed = 12 MBps  HS = High Speed = 480 MBps.10:49
tntyou can do LS and FS using normal IO pins/CMOS drivers.10:49
tntfor HS you need a dedicated PHY chip.10:49
corecodei wonder whether a HS USB SIE done using a softcore would be smaller and easier to maintain than a monolithic design11:12
promachSIE ?11:16
corecodeserial interface engine11:16
MoeIcenowyI heard that Lattice claims USB on Lattice FPGAs w/o ext PHY is not possible11:19
corecodebecause they didn't certify it for usb11:20
tntcorecode: what do you mean monolithic ?11:22
tntOh. Well it's not HS (only FS), but ATM I'm doing a USB core that implements the 'usb stack' in a CPU. Much like you would find an common microcontroller. Packet level stuff is done in hardcoded logic. Transaction stuff is done in a microprogrammed state machine, and then the higher "transfer" layer is left to the CPU to do.11:24
corecodethe SIE11:24
corecodeare you doing a HS SIE?11:25
corecodei don't know too much about HS frames11:25
tntno, FS only. I don't want an external PHY.11:25
corecodeis there much to do even?11:26
MoeIcenowyI think USBASP is some USB LS implemented in software with 8-bit AVR...11:26
MoeIcenowyit astonished me11:26
corecodereceive packet id, address, buffer out, checksum, ack?11:26
tntcorecode: for HS you mean ?11:27
corecodethat needs to be in the fast loop11:27
corecodei think you only have so many bit times to answer ack/nak11:27
tntThe transaction layer needs to be fast, you only have 6.5 bit time to respond in FS.11:27
tntSo when you get a IN or OUT token, you have to decide fast what to answer.11:28
corecoderight, so that needs to be in a register already11:28
MoeIcenowymaybe implementing LS will be more loose?11:28
corecodeLS will be the same, just slower11:28
MoeIcenowyUSB is too strict!11:29
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tntcorecode: yeah, I have basically just enough time to fetch from RAM the endpoint status and start the reply. That's why the transaction layer is still done in 'logic' (ok, microprogrammed, but still not quite a generic CPU) and not by just the soft core.11:30
corecodeah you don't keep the EP in registers?11:30
tntNo, I keep buffer rings in a RAM.11:31
tntAnd fetch/writeback when starting/finishing the transaction.11:31
tntI wanted to be able to handle many endpoints without too much overhead.11:31
corecodeyea i understand11:32
tntAlthough technically you can only have 16 endpoints :/11:33
corecodealso, bidirectional11:34
corecodeplus multiple buffers11:34
tntThe EP field is 4 bits11:34
tntOh yeah, endp numbers can be re-used for IN/OUT.11:35
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tntdaveshah: any idea where I could find a example for that dual clock / different width ? Pretty much everything I tried resulted in ... no RAM :p11:47
tntmm, actually from what I read, I don't see that yosys can infer READ_MODE != WRITE_MODE11:55
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daveshahno, although some quick tests and it's happy to fake it with logic and the mask input11:56
tpbTitle: Snippet | IRCCloud (at
MoeIcenowyBTW is it possible to implement ADC with iCE40?11:58
daveshahMoeIcenowy: yes, probably11:58
daveshaheither doing something like charge time measurement of a capacitor, or sigma-delta with a diff input as a comparator11:59
MoeIcenowyI think some AN of Lattice mentioned it on ECP and XO series11:59
MoeIcenowyit should apply to iCE11:59
tntgoogle "Common Analog Functions Using an iCE40 FPGA", first result.12:00
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tnt(couldn't ... ungooglify the link ...)12:00
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tntAh well, I managed :p12:02
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corecodedoesn't this take quite some space on the fpga?12:23
tntDAC ? not so much. ADC a bit more since you need the CIC but depends what kind of rate / precision you want.12:43
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promach2corecode : is it difficult to write a USB softcore from scratch ?14:35
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corecodei don't know14:37
corecodei've only written the protocol part, not the bit part14:38
promach2bit part ?14:40
corecodelayer 0 and 1 stuff14:44
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promach2corecode : you don't need to do the physical layer part14:46
promach2why would you ?14:46
corecodeyou don't need anything, you can buy everything completed14:47
promach2no offense. I mean the physical layer involves IO analog circuitry, that requires tapeout14:50
corecodeusb LS and FS can be done with gpios14:50
promach2and what exactly do you mean by "layer 0 and 1"  ?14:51
daveshahthe tinyfpga does it with a grand total of three resistors, the rest being done with FPGA pins14:51
promach2two series resistors and one pull-up14:51
promach2what exactly is  "layer 0 and 1"  ?14:56
promach2I have been reading the official USB 2.0 spec , but there is no mention of that so far14:57
MoeIcenowydaveshah: is the resistor value critical?14:57
promach2MoeIcenowy : see
tpbTitle: Extra resistor on FPGA transmitter pin · Issue #1 · avakar/usbcorev · GitHub (at
daveshahThe 1.5k should be reasonably accurate, iirc, but I don't know about the 68r one14:57
corecodepromach2: sorry, i mean layer 1 and layer 2 (osi model)14:59
promach2corecode : so, you are working on layer 2 (data link layer) now ?15:01
corecodepromach2: i.e. physical layer (electrical) and data link15:01
corecodei am not working on anything15:01
promach2so, you had done implementing chapter 8 of USB 2.0 spec15:01
promach2now only left with chapter 515:02
MoeIcenowyI mean the 68r ;-)15:02
MoeIcenowythe SMT service where I use (JLC SMT) doesn't offer 0402 68R15:02
corecodepromach2: what are you talking about15:03
corecodewhich 68R15:03
corecodejlc offers pcba?15:03
MoeIcenowycorecode: not full PCBA15:04
MoeIcenowyonly the SMT of specified components15:04
promach2corecode : chapter 8 is protocol layer , chapter 5 is data flow model15:04
MoeIcenowyand only available in Chinese15:05
promach2corecode : USB 2.0 spec15:05
MoeIcenowybut with it I can use 0402 components...15:05
MoeIcenowyI don't dare to solder them by myself...15:05
promach2corecode : see
tpbTitle: USB in a NutShell - Chapter 1 - Introduction (at
corecodei know usb15:05
promach2MoeIcenowy : no worry, with few weeks of practice, you could do 0201 with only soldering gun under few seconds15:06
corecodepromach2: what are you working on?15:06
promach2corecode : huh ?15:06
MoeIcenowypromach2: I have no soldering gun15:06
MoeIcenowyonly soldering iron15:07
promach2same thing15:07
corecodepromach2: what project are you working on?15:08
corecodeyou seem to be doing usb, network on chip, etc.15:08
MoeIcenowyoh I thought you meant heating gun15:08
promach2no, you do not need hot-air gun15:08
corecodehot air station is important15:08
corecodeand cheap15:08
promach2soldering iron is way cheaper15:09
promach2and precise15:09
corecodegood one not15:09
promach2corecode : going to start on usb once I am done with NoC15:10
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corecodeis this for work or a hobby?15:14
MoeIcenowyI'm thinking whether I will be able to solder iCE40UP5K-SG48I with soldering iron15:16
daveshahThe exposed pad will be tricky, and can't be skipped because it's the only grounding15:16
MoeIcenowydaveshah: I reserved a through hole for it15:17
emebthat's what kevin hubbard does - great big hole in middle of the exposed pad15:18
emebfill in w/ solder from the back15:18
emebI just use paste + hot air to solder those QFNs15:18
corecodeMoeIcenowy: no, use hot air15:19
MoeIcenowyI remember once I got a free unsoldered GD32F150G8U6 board from JLC15:19
MoeIcenowyand finally I disposed it15:19
corecodeyou don't need paste, but you need hot air15:19
MoeIcenowyas I found I'm not able to solder the exposed pad of GD32F150G8U615:19
MoeIcenowymy table is too small to keep a hot air gun...15:20
corecodei guess you can find some solder ninja just around the corner15:21
emebcorecode: so all your u4k work got accepted into mainline?15:23
* emeb goes to pull & rebuild15:25
promach2u4k ?15:28
emebolder lattice ice40 ultra stuffs15:29
cr1901_modernAhhh someone was gonna offer me hardware to do ultra RE, but I got too busy. Nice work15:53
cr1901_modernis ultralight still up for grabs?15:53
daveshahcr1901_modern: yeah ultralite still available15:54
daveshahhappy to pay for hw too15:54
cr1901_modernhmmm tempting. (for the record, someone _else_ was gonna offer me h/w, but they're on social media break atm)15:55
cr1901_modernI've been trying to coordinate w/ Andres, but the times we are awake/active don't seem to coincide15:55
cr1901_moderncorecode: You did just the 4k family of ultra?15:56
daveshahthere is only the ultra 4k15:56
daveshahthe other parts are pseudo-devices15:57
daveshahditto there is only one ultralite15:57
cr1901_modernahhh, well ultralite is about machxo2-1200 level of complexity15:57
daveshahyeah, although probably less fuzzer hacking needed as I think it is closer to the ice40up than the xo2 is to the ecp515:58
cr1901_modernlet me touch base w/ andres.16:00
cr1901_moderncorecode: MachXO2 is probably going to reach a point of usability soon. Would be happy to help w/ ultralite if you want to do it (or start it myself when machxo2 reaches minimum viable product).16:00
emebdaveshah: is u4k also in yosys & nextpnr?16:02
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MoeIcenowyis someone doing MXO2 RE?16:21
cr1901_modernMoeIcenowy: Me, technically but it's stalled due to chronic "I can't multitask"-itis16:26
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corecodeif you're going to put in dozens of hours for reversing, $30 for an eval board is negligible17:02
MoeIcenowyI think I have seen some LCMXO2-4000HC-4MG132 board for CNY ¥16917:07
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emebalways fun when building yosys to get to the 95% point where ABC takes the other 95% of the time. :)17:53
shaprI can build yosys so fast on my new laptop... now if I only had some clue about verilog18:10
shapreven the most powerful hardware does not increase my skills all by itself18:11
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emeblots to learn18:32
emebcorecode: daveshah: trying to build a simple blinky for u4k. yosys seems to work but nextpnr gives Fatal error: file not found --u4k18:33
emebwhen i do --help for nextpnr it lists --u4k as a device option though. what am I doing wrong?18:34
daveshahemeb: what is your full command line?18:34
emebnextpnr-ice40 --pcf-allow-unconstrained --pre-pack  --u4k --json bob_blinky.json --pcf ../src/bob_blinky.pcf --asc bob_blinky.asc18:35
daveshah--u4k shouldn't be after --pre-pack18:35
daveshah--pre-pack file runs a Python file before packing18:35
daveshahUsually for constraints18:35
daveshahSo it's interpreting --u4k as a file18:36
emebdaveshah: ok - I see what's wrong. missing the constraint file define in my makefile. derp.18:37
emebdaveshah: is there a place I can look which tells me what cells a particular target FPGA family supports?18:39
emebeg - what's the name of the RGB driver in u4k18:39
emebsince it's not the same as in up5k18:40
emeband doesn't match up with what icecube2 uses.18:40
daveshahNo, I made that for ECP5 but nothing like that exists for ice40 other than vendor documentation18:40
daveshahAsk corecode but I don't think the u4k rgb is supported in nextpnr yet18:40
emebcorecode: do you implement the RGB driver in u4k?18:41
emebif so, what's it called?18:41
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tntDoes anyone see anything wrong with that functions :19:01
tpbTitle: function [15:0] ram_wr_map2 (wire [1:0] wdata); ram_wr_map2 = { - (at
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emebnothing obvious to me19:19
tntarf, you need 'input wire' and not just 'wire' ....19:22
ylamarre... VHDL has a nice "feature for this kind of assignement where you can assign parts of a signal then give a "default value" to others....19:29
* ylamarre wonders if nMigen and/or MyHDL have this feature...19:30
tntylamarre: oh yeah right. tbh I mostly used that to assign 0 to the whole verctor :p x <= (others => '0'); :p19:41
ylamarreYes, but you can also do weird slices that way too.19:42
ylamarreMost missed feature when I had to transfer to verilog.19:43
tntDamnit, iverilog doesn't like my function either ... syntax error :/19:44
tnt'input wire' -> 'input'19:47
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tntMmm, yosys doesn't seem to like the 'new style' of having the reset at the end of the process when using a 'case' and an async reset :
tpbTitle: always @(posedge clk or posedge rst) begin case (d) - (at
tntERROR: Multiple edge sensitive events found for this signal!20:10
emebI remember Clifford advocating for the "reset at end" style. Interesting that yosys doesn't like it sometimes.20:20
ylamarreLooks like it's more about the always block then the reset location...20:25
ylamarreCoded this way it looks like you have two clocks.20:25
tpbTitle: module test( input wire d, output reg q, input wire clk, input wire rst - (at
tntthis is the other variant that works fine.20:29
daveshahtnt: I don't think the first code is legal Verilog for synthesis20:31
daveshahsee p9 of
tntdaveshah: Ok, indeed, so it's not yosys specific. It's just that in verilog with async reset you don't have a choice you _must_ use the legacy style resets. Good to know.20:37
tntTIL :)20:38
daveshahHowever, aiui, async reset blocks don't have the "not putting a signal in the reset block makes reset a clock enable instead of just ignoring reset" problem as with sync resets20:43
daveshahso the only problem is inconsistency, the actual advantage of the reset at end style isn't present20:43
tntYeah, I was going for consistency :)  But I never do process that have mixed reset/non-reset signals anyway, so the 'end style' is really just a 'style' for me ... no actual benefit.20:46
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corecodecan you explain?23:52

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