Saturday, 2019-02-23

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MoeIcenowyhow much current will an iCE40UP5K cost at most?13:48
tntlike 10-20 mA 1.2v core current at the _very_ most.13:52
tntfor the IO ... well, that's mostly whatever you connect on those IO.13:53
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tntI have no idea if it's even doable, but I wish there was a way to tell yosys to not create a different control set (i.e. Clk / CE / Set/Reset) for the bits of a same vector create from the same verilog statement.15:13
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tntIt's virtually never what I want.15:13
tnt"Great you saved 1 LUT4 by using the Set/Reset ... but (1) it's not really saved because the LUT4 is there anyway and has to be used as pass through  (2) now the entire PLB is used up by 1 LC because that controlset is not used anywhere else"15:15
corecode\o/ the bin works!16:15
corecodefinally i can unrecurse my yak16:16
corecodeand get on with my cpu design16:17
corecodetnt: what would you like to see instead?16:17
corecodedaveshah: is there anything else i need to do for these PRs, or do we just wait until somebody commits?16:33
daveshahI'll get clifford to review the icestorm one, then merge the nextpnr one once that's done16:34
tntcorecode: well instead of using the 'set' line, it could pack an OR in the LUT4 before the FF.16:35
corecodeif it is a sync set16:36
tntit is.16:36
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tntAnd in another instance, for some reason, it decided to use the CE line instead of a MUX with previous value for a _single_ bit of a 12 bit vector ... (even though it doesn't save anything, the LUT4 before that FF could be used for that with no overhead).16:37
corecodeisn't that a thing the placer also needs to have a say in?16:37
tntthe synth does the LUT packing, so it should know that this fits inside the LUT preceding the FF.16:38
daveshahIt wouldn't be a big pass to unpack CE/SR if (a) the FF is driven by a LUT with spare inputs or (b) the FF is driven by a non-LUT or LUT with fanout >116:39
daveshahnot that I have time to write it any time soon16:39
corecodewhy fanout>1?16:40
daveshahsomewhat arbitrarily we separate the FF from the LUT in these cases rather than duplicating the LUT16:41
daveshahprobably slightly reduces routing congestion, as only one signal to route rather than 1-416:41
corecodeah, the DFF can only receive input from the LUT out?16:41
daveshahunlike most other FPGA arches16:42
corecodei see16:42
corecodewho inserts the passthrough LUT?16:42
corecodebut if you wrote a pass to check for LUT out > 1, you might as well do it in yosys?16:42
daveshahcorecode: icestorm PR is merged16:43
daveshahcan you update in your branch so that nextpnr CI should pass?16:44
tpbTitle: nextpnr/Dockerfile.ubuntu16.04 at master · YosysHQ/nextpnr · GitHub (at
tntdaveshah: thing is, I'd mostly like that decision to be based on the full vector rather than individual bits, to avoid creating different control sets.16:44
corecodewill do16:44
corecodetnt: because of timing?16:51
tntcorecode: because I don't want to waste PLBs16:52
corecodefor a vector you have the advantage of sharing the signals tho16:52
tntcorecode: LCs with different control set can't be packed in the same PLB.16:52
MoeIcenowydaveshah: how to estimate how much power will iCE40 drain?16:53
daveshahI think Lattice have a tool somewhere16:53
MoeIcenowyI'm considering to make a board with small-size LDO16:53
daveshahthe answer is not much :)16:53
MoeIcenowydaveshah: is there an upper bonud16:53
MoeIcenowybound *16:53
daveshahfor the up5k? 30mA16:53
MoeIcenowythe datasheet says booting peak current16:53
MoeIcenowybut no highest operation current16:54
daveshahno, that's quite hard to specify16:54
MoeIcenowymaybe I should download the design checklist by Lattice?16:54
tntMoeIcenowy: the icebreaker uses sot-23 linear regulators.16:55
daveshahfwiw, MARLANN (simple CNN accelerator) using all DSPs, SPRAM and majority of LUTs at 20MHz consumes 14mA Vcore16:56
daveshahgoing above 40MHz for a large design would be very hard, so that would give about 30mA max16:56
corecodeMoeIcenowy: yea, also understand difference between core and IO current16:59
MoeIcenowytnt: okay ;-)16:59
MoeIcenowyseems that 200mA is enough?16:59
corecodefor what rail17:00
daveshahIf it draws 200mA Vcore it is probably dead :P17:00
daveshahIO pins are 8mA nominal max current, so max for all 36 non-open-drain pins is 288mA, but that's quite a crazy case17:00
corecodei use a mic5504-1.2 fwiw17:01
tntdaveshah: or like me you soldered it 90deg off :p17:01
corecodedaveshah: yea but isn't switching current higher?17:01
daveshahcorecode: maybe a bit, probably not that significant at iCE40 freqs and slew rates though17:01
corecodewell, knowing the application + math = success17:02
MoeIcenowytnt: is your chip still alive?17:02
MoeIcenowyor does it rest in peace?17:02
tntMoeIcenowy: it survived just fine :)17:03
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corecodeimaginary current17:08
MoeIcenowyoh as a Computer Science student I know none about imaginary in circuits17:19
corecodeit's a joke17:20
corecodebecause the chip was 90 degree offset17:20
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corecodehm, syntax error21:16
corecodetop.v:39: ERROR: syntax error, unexpected ATTR_END, expecting TOK_ID21:17
corecodei can't use catch all signal assignments?21:17
daveshahsounds like systemverilog21:17
daveshahwhat does your code look like?21:17
corecodemodule instantiation with  , .*);21:18
corecodehm i guess everybody else accepted it21:18
daveshahyeah, that's valid systemverilog only21:18
corecodeeven with -sv yosys doesn't like it21:19
daveshahno, yosys only has limited sv support right now21:20
corecodei wonder whether some emacs autoparam magic will do the right thing21:20
corecodea: yes.21:22
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corecodesomehow i can't get verilog-mode to align my hand written ports in an instantiation21:54
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corecodeso what's the suggested way to design a POR23:18
ZipCPUreg por; initial por = 1'b1; always @(posedge i_clk)  por <= 1'b0;23:21
corecodeah, synchronous23:22
corecodeyea i had something like that, just more complicated with multiple shifts23:22
corecodehm, now only 28MHZ?23:30
corecodeso how come icecube says clock frequency 47MHz23:37
corecodeand nextpnr says 28MHz23:37
corecodebut then, icecube can't place my ram, so...23:37
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corecodehow do i read this slack histogram?23:44

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