Wednesday, 2019-02-20

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chaseemoryZipCPU, i managed to get the Ethernet port working on the Nexys Video, it was a mixture of a few issues, wireshark came in super handy01:25
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ZipCPUchaseemory: Can you tell me what you used for the clock on the transmitter?01:32
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chaseemoryi made two 125MHz clocks in an mmcm, one 90degrees out of phase, i dug through the layers of the code in the repo and thats the clock it seems to be using for the tx_clk01:46
tpbTitle: verilog-ethernet/rgmii_phy_if.v at master · alexforencich/verilog-ethernet · GitHub (at
ZipCPUThanks!  I'll take a peek01:48
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mithroZipCPU: You should tell chaseemory about liteeth - it already supports GigE on Nexys Video plus a bunch of other stuff too05:45
mithroZipCPU: _florent_ was getting liteeth working on the ECP5 too05:45
MoeIcenowybought an EP4CE115 board with DDR2 SO-DIMM connector06:12
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MoeIcenowyseems that utilizing DDR memory is a disaster...06:13
MoeIcenowy(I do not like vendor IP06:13
sorearactually having a DIMM connector is good06:13
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MoeIcenowysorear: yes, it's easily replaceable memory ;-)09:48
MoeIcenowyI love the connector09:48
MoeIcenowybut I don't love to utilize DDR on FPGA09:48
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corecodedaveshah: ok, i think the last thing is to fill the extra_cells_db10:27
daveshahcorecode: yeah10:29
daveshahfor SB_WARMBOOT, create one and trace the routing in icebox_vlog10:29
daveshahfor the remaining IP, hopefully the script for the UltraPlus is adaptable10:29
corecodewarmboot i already handled10:30
corecodewell, i'll skip the i2c and spi for now10:31
corecodebut hfosc and lfosc is important10:31
corecodei guess there is no test fixture for it yet10:33
corecodewhat's the easiest way to figure out where config bits sit?10:34
corecodeset them and look in the explanation?10:34
MoeIcenowyoh my laptop's LCD screen is too small in points to use the DDR2 controller IP from Quartus ;-)10:38
corecodedaveshah: do i have to modify the standard cell library to access the TRIM input?10:53
corecodehuh, icecube says "no top-level module"11:13
corecodewhat's that about11:13
corecodefound it11:14
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corecodedaveshah: trying to find the extra_cells for the hfosc - how do i know the location of the CLKHF output?  i used it for a SB_IO output clock, but vlog says:11:31
corecodewire io_19_31_0;11:31
corecode// (0, 0, 'glb_netwk_4')11:31
corecode// (9, 31, 'io_global/outclk')11:31
corecode// (19, 31, 'io_0/PAD')11:31
corecode// (19, 31, 'padin_0')11:31
corecodeis (0, 0) credible there?11:31
daveshahyes, it is global network glb_netwk_411:31
daveshahrouted through the padin of 19, 3111:31
corecodebecause on the 5k it is (0, 29)11:32
daveshahthe global networks are really in every tile, so it doesn't matter11:32
daveshahit's the glb_netwk_4 that's important11:32
corecodehm, why doesn't vlog show the HFOSC11:33
daveshahit doesn't support them11:33
corecodeaha :)11:33
corecodehm, i thought HFOSC was global network 5 according to docs11:44
daveshahwouldn't be the first mistake in Lattice docs11:48
daveshahit's glb_netwk_4 on the up5k too11:49
corecodeis that different from some other global buffer stuff?11:49
daveshahthe only difference is the SB_GB driving a different glb_netwk_i to the SB_GB_IO/padin at the same location11:50
corecodenow i question my padin_io and padin_glb_netwk11:50
corecodeso the HFOSC is global network 4, but routed via padin_glb_netwk 5?11:55
corecodeor is that output of icebox_explain just what i did11:55
daveshahthe HFOSC is global network 4 plain and simple11:55
daveshahthis is entirely padin11:55
corecodeok, so i need to switch those two around11:57
daveshahwhich two?11:57
corecodeHF and LF padin11:57
corecodeok i need to redo my gbufin11:59
corecodei had some bogus data on it which confused me12:00
daveshahthe important thing gbufin is totally unrelated to padin12:00
daveshahit's just coincidental that the locations are the same12:00
corecodeespecially if i cannot trust the ice docs12:00
corecodewhich means my explain output is unreliable as well12:00
daveshahno, the explain output will always be correct12:01
daveshahit doesn't rely on gbufin or padin at all12:01
corecodefor the extra bits it uses the extra bit info12:01
corecodewhich was wrong for me12:01
daveshahah, right12:01
daveshahinside logic, IO tiles, etc the glb_netwk_* will always be correct though12:01
daveshahthey are based on the low level routing bits determined by icefuzz and the glb files12:02
corecodeok, i'm looking at gbufin right now12:03
corecodei have clk on pin 4412:03
corecodewhich the docs say is G612:03
daveshahThe global numbers for the docs are for padin12:03
daveshahnot gbufin12:03
corecodewhat?  how would that be useful12:04
daveshahi.e. the global numbers in the docs (if they are correct) will only apply if using SB_GB_IO12:04
daveshahSB_GB are driven from fabric rather than an IO pin12:04
corecodeyes, i thought gbufin is from the outside12:04
daveshahno, gbufin is for SB_GBs from fabric12:04
corecodegod damn, these names are so confusing12:04
daveshahpadin is for SB_GB_IOs from the IO pins12:04
corecodealright, back to padin12:05
daveshahbeware that connecting to a SB_GB to a pin doesn't guarantee that icecube will place that GB next to the pin (unlike an SB_GB_IO)12:05
corecodeso i have a sb_gb_io, and explain says it uses glb_netwk_112:05
corecodebut the docs say it is G612:06
daveshahthis is inside a logic/io tile and not extra bits?12:06
corecodeit also sets extra bits12:06
daveshahignore the extra bits for now, just look at the routing in logic/io tiles12:06
corecodeshould i use explain or vlog?12:07
daveshahalso, extra bitS or just one extra bit?12:07
daveshahcan you post the explain output?12:07
corecodebuffer glb_netwk_1 io_global/outclk12:07
tpbTitle: glb_u4k_pin_44.tcl · GitHub (at
daveshahso that is driving glb_netwk_1 for sure (and it looks like your extra bits database is wrong)12:09
daveshahthat is coming from IO (6, 0, 1)?12:09
daveshahIO (6, 0, 1) also drives glb_netwk_1 on the up5k12:10
corecodewhere do you get (6, 0, 1) from?12:11
daveshahIE_0 in io_tile 6, 012:11
daveshahIE_0 corresponds to pin z 1 because of the swapped ierens12:11
corecodethey're swapped on one side?12:12
daveshahboth sides according to your ieren db12:13
daveshahwhich also matches the ultraplus12:13
daveshahthis only applies to the IE/REN bits in icebox_explain12:14
daveshaheverywhere else should use the normal, unswapped values12:14
daveshahlooking at the Lattice docs, I think Lattice themselves were confused between gbufin/padin12:14
daveshahThe UltraPlus docs and pinout by Lattice give padin numbers for IO, which makes sense12:14
daveshahit looks like some of the Ultra docs give gbufin numbers for locations12:15
corecodeokay, so i corrected the 4 pins i have12:17
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corecodedaveshah: i guess for the timing generation i first need yosys to work with the part?15:40
tpbTitle: iCE40 Ultra = iCE5LP = u4k port by corecode · Pull Request #202 · cliffordwolf/icestorm · GitHub (at
* sxpert uses alien on diamond's rpm...15:45
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MoeIcenowysxpert: sigh15:50
MoeIcenowyis Diamond only available in RPM?15:50
corecodewhat else15:50
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sxpertMoeIcenowy: yeah15:51
sxpert"for redhat enterprise linux blah"15:51
sxpertand then you have the stupid licensing stuff which I have yet to figure out15:52
corecodei somehow had to create an alias for eth015:52
MoeIcenowyI disabled the NIC renaming to run iCEcube215:52
corecodeah that's what it was15:52
sxpertoh, and they can't seem to be bothered to roll all their patches in one single file, you have to install a separate sp3 package... sigh15:52
sxpertcorecode: does it REQUIRES an eth0 ?15:53
sxpertor do you need something else ?15:53
corecodeand it might have been icecube15:53
sxpertah, ok, all set then15:54
sxpertobviously, you could just popup a virtual eth card with a bogus mac15:54
somloor, even better, "tunctl -t eth0"15:55
somloit'll be there, but do nothing (other than shut up Vivado or Diamond or whatever is looking for it ) :)15:55
sxpertheh yeah15:56
daveshahcorecode: The changes to Yosys will be minimal15:59
sxpertah, they can't seem to be bothered to provide a menuentry file15:59
daveshahcorecode: just adding blackboxes (i.e. verilog with only ports and parameters) for any new IP to
tpbTitle: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at
sxpertbouahahaha "I verify that I am not an employee of Cadence Design Systems, Mentor Graphics Corporation, or Magma Design Automation"16:04
sxperthmm, the service pack .deb is installed, and the stupid thing doesn't see it16:12
MoeIcenowyI wonder whether the "adaptive" license process of Lattice can prevent any piracy16:13
sxpertwierd, I have both packages installed... where is the SP3 ?16:14
sxpertquality software detected ;-)16:15
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corecodedaveshah: i'd love to get some feedback on the PR:
tpbTitle: iCE40 Ultra = iCE5LP = u4k port by corecode · Pull Request #202 · cliffordwolf/icestorm · GitHub (at
daveshahcorecode: sure17:56
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corecode    seq_bits = icebox.get_lutff_seq_bits(ic.logic_tiles[(lut[0], lut[1])], lut[2])18:09
corecodeKeyError: (25, 19)18:09
corecodewhere did it get that from18:09
corecodeyea, where does this ipcon_tile 25 19 come from18:13
corecodewhy can't it find that logic tile?  because it is not a logic tile18:14
MoeIcenowymaybe someday I should try out a UL port?18:14
corecodeyea if you have parts18:15
MoeIcenowysomeone sells UL core board at Taobao for CNY ¥30 (~USD 5)18:15
MoeIcenowyalthough I think it has too few IOs18:15
corecodewell, i have a design that uses the u4k18:16
corecode1k actually18:16
corecodehow do i know which CBITs are set in a tile?18:22
corecodei see bits set in dsp3_tile 0 1618:22
corecodebut i don't know how B2[7] translates to CBIT_3 or CBIT_418:23
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daveshahcorecode:  so this would be looked up in the bit database built by icefuzz18:36
tpbTitle: icestorm/ at master · cliffordwolf/icestorm · GitHub (at
daveshahistr this bit doesn't exist in the database for dsp3_tile because there was no way to set it in icecube18:37
daveshahthe ultimate solution is to try and add whatever is setting this bit to and rerunning the fuzzer18:38
daveshahthen it will end up in the database as CBIT_x properly18:38
corecodewhy is this part of the dsp2 database?18:43
corecodedoes it just happen to sit there?18:44
daveshahno, I was using the dsp2 database as an example18:51
daveshahatm it exists only in the dsp2 database18:51
daveshahit should be in the dsp3 database too, but isn't because there was no way to set it on the ultraplus so icefuzz didn't add it18:52
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MoeIcenowyoh my god19:23
MoeIcenowythe ddr phy of Altera is not standard DFI19:24
MoeIcenowybut AFI (Altera PHY Interface) instead19:24
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