Tuesday, 2019-02-19

*** tpb has joined #yosys00:00
corecodedaveshah: i don't seem to find a way to specify a global buffer network00:07
corecodeonly promote/demote00:07
daveshahUse a manually placed SB_GB00:09
corecodeyea, doing that now00:09
corecodewell, 800:09
corecodeotherwise it keeps placing it in the same location00:10
daveshahI'm pretty sure you can override this in floorplan view or the PCF file00:12
*** Thorn has quit IRC00:12
daveshahSomething like set_location name x y z00:12
corecodewell, i'm trying to figure out the gb locations00:13
corecodebut this seems to have worked00:13
daveshahYou can see them in floorplan view00:13
daveshahAt some point you'll probably need to create them one by one to find out which network each fabout drives00:14
corecodei just created 8 inputs, 8 SB_GB, 8 outputs00:14
corecodehm, how would i know?00:15
daveshahBy creating them one by one manually placed at each location00:15
corecodeif i cannot constrain it to a network, i constrain it to a location00:16
corecodeand then it has to be that network00:16
daveshahAnd seeing which glb_netwk appears in the icebox_explain output00:16
corecodedoesn't explain use the data that i'm trying to fill in?00:16
daveshahNot this data00:16
daveshahicebox_vlog does00:17
daveshahicebox_explain is lower level, all it needs is the list of tiles and the actual bitstream bit mapping00:17
corecodeah no00:18
corecodei can see both00:18
corecodethe explain shows me the network number00:18
corecodeand given the output, i know what input clock it was00:18
daveshahYeah, that works00:19
corecodedoes the order matter in gbufin_db?00:25
daveshahNo, but it does for padin_db00:26
corecodewhat about the location within the tile? the 0 1, does that not matter for the gbufin?00:27
daveshahNo, it doesn't00:28
daveshahI think it is always 2, but that isn't used anywhere00:28
corecodethe psb shows00:29
corecodeset_io gbufin_3 6 0 1 # ICE_GB00:29
corecodenot always 1 though00:29
daveshahYeah, that's fine00:30
corecodefor my fake padin, does it matter there?00:30
daveshahNo, it doesn't00:31
*** pie_ has joined #yosys00:32
corecodehm, vlog fails with nonexistant data00:47
corecodesomething in get_pll_bits00:47
*** emeb_mac has joined #yosys00:57
*** cr1901_modern has quit IRC00:59
corecodedaveshah: what do you mean by "So a tiny bit of semi-manual work is needed #first to discover this (basically run this script with show_all_bits=True #and look for the stuck bit"01:01
corecoderun it completely?01:01
corecodei guess i'll see01:01
* corecode waits for fuzzing to end01:01
*** emeb has quit IRC01:02
*** cr1901_modern has joined #yosys01:23
*** cr1901_modern has quit IRC01:48
*** jevinskie has joined #yosys01:55
*** gsi_ has joined #yosys02:04
*** gsi__ has quit IRC02:07
*** gsi_ has quit IRC02:20
*** cr1901_modern has joined #yosys02:45
*** seldridge has quit IRC03:15
*** citypw has joined #yosys04:04
*** citypw has quit IRC04:05
*** rohitksingh_work has joined #yosys04:07
*** citypw has joined #yosys04:12
*** pie__ has joined #yosys04:13
*** pie_ has quit IRC04:15
*** gsi_ has joined #yosys04:36
*** leviathanch has joined #yosys04:41
*** proteusguy has joined #yosys05:50
*** chaseemory has quit IRC06:07
*** awordnot has quit IRC06:32
*** awordnot has joined #yosys06:35
*** emeb_mac has quit IRC07:14
*** dys has quit IRC07:43
*** cr1901_modern has quit IRC07:55
*** cr1901_modern has joined #yosys07:56
*** jevinskie has quit IRC08:22
*** s_frit has joined #yosys08:25
*** m4ssi has joined #yosys08:40
*** pie_ has joined #yosys08:57
*** pie__ has quit IRC08:59
*** m_t has joined #yosys09:07
*** danieljabailey has quit IRC09:37
*** Thorn has joined #yosys10:00
*** leviathanch has quit IRC10:02
*** citypw has quit IRC10:21
*** Thorn has quit IRC10:26
*** flaviusb has joined #yosys10:33
corecodegotta figure out where all these PLL ports come from11:30
daveshahcorecode: icebox_vlog will tell you that12:26
daveshahJust connect each port to a pin and see where the routing for that pin ends up12:26
corecodeyea, icebox_vlog still crashes based on missing data :)12:26
corecodebut getting there12:27
corecodeneed to input the iolatch data12:27
daveshahsure, just fill in any old stuff to get icebox_vlog working, even comment it out12:32
daveshahThere should be a script for the iolatch data12:32
*** Thorn has joined #yosys12:35
*** rohitksingh_work has quit IRC12:55
*** m_t has quit IRC13:11
*** AlexDaniel has quit IRC13:21
*** jevinskie has joined #yosys13:47
*** tlwoerner has quit IRC13:51
*** rohitksingh has joined #yosys13:52
*** danieljabailey has joined #yosys14:01
*** somlo has quit IRC14:42
*** tlwoerner has joined #yosys14:42
*** leviathanch has joined #yosys14:47
*** develonepi3 has quit IRC15:10
*** jevinskie has quit IRC15:34
*** rohitksingh has quit IRC15:39
*** citypw has joined #yosys15:44
*** seldridge has joined #yosys15:46
*** develonepi3 has joined #yosys15:49
sxpertZipCPU: have some time for constructive criticism ? https://github.com/sxpert/hp-saturn/blob/master/saturn_bus_ctrl.v16:00
tpbTitle: hp-saturn/saturn_bus_ctrl.v at master · sxpert/hp-saturn · GitHub (at github.com)16:00
corecodewhy [0:0]?16:01
sxpertbecause I get complaints about dimentions not set16:02
corecodeso what are you working on?16:03
tpbTitle: Saturn - Wikipedia (at en.wikipedia.org)16:03
sxpertah, hmm, bad link ;)16:03
tpbTitle: HP Saturn - Wikipedia (at en.wikipedia.org)16:04
ZipCPUsxpert: You are missing the `default_nettype none instruction at the top ;)16:04
ZipCPUYou have several unused signals: i_en_bus_recv, i_en_bus_ecmd, i_alu_pc, i_read_pc, i_cmd_dp_read ...16:05
ZipCPUOh, and almost forgot i_en_bus_send16:06
* ZipCPU is running a verilator -Wall check16:06
sxpertthose are goners16:06
corecodeis that the original bus?16:06
sxpertcorecode: yes16:06
*** rohitksingh has joined #yosys16:07
sxperttheoretically the 4 datalines are bi-directionnal, but that may be impossible depending on the fpga16:07
ZipCPUYou can turn the "noise" off by wrapping their definitions with "// verilator lint_off UNUSED" and "// verilator lint_on UNUSED".  Alternatively, you can create one big unused chunk at the bottom with, "wire [N-1:0] unused; assign unused = { your_uused_wires };" and then wrap it with the Verilator lint statements16:07
ZipCPU(Replace N with the number of wires that are unused)16:08
sxpertno no, I ough to remove those unused signals, just didn't get to that yet16:08
ZipCPUThat works too16:09
sxpertbeen furioulsy rewriting that thing 3 times or so ;)16:09
ZipCPUStill needs formal properties16:09
sxpertZipCPU: well have to understand how that works first16:10
corecodeyea me too16:10
*** somlo has joined #yosys16:40
*** citypw has quit IRC17:24
corecodedaveshah: so what now?17:28
corecodei think i'm almost done17:28
corecodejust need to do some pll port testing17:28
daveshahNext step is to make sure that icebox_chipdb generates the text database for arachne/nextpnr17:28
*** m4ssi has quit IRC17:33
corecodenow i just need to see what signal is actually routed to the respective fabout locations17:37
corecodefor the pll ports17:38
*** emeb has joined #yosys17:43
corecodehow do i best trace the routing?17:46
daveshahcorecode: just create a design with all the PLL pins connected to top IOs and run with icebox_vlog17:53
daveshahpassing the PCF to icebox_vlog so it picks up port names too17:53
*** leviathanch has quit IRC17:54
*** rohitksingh has quit IRC19:12
*** dys has joined #yosys19:18
*** vzcx has joined #yosys19:37
vzcxhas anyone had success using yosys/icestorm on openbsd?19:37
ZipCPUAre you struggling with anything in particular?19:38
vzcxi'm having trouble flashing my hx8k... seems to raise an error in libusb19:38
vzcxwhen using iceprog19:38
ZipCPUDoes it build without problems?19:39
vzcxthe iceprog tool? yes.19:41
ZipCPUWhat error do you get?19:42
vzcxusb_bulk_write failed19:42
vzcxthis happens at the first call to send_byte, at the line commented "enable clock divide by 5"19:43
* ZipCPU doesn't have openbsd, and is struggling to know what to ask next19:45
* vzcx knows disappointingly little about ftdi, hardware generally, and what's supposed to be happening here19:46
*** dys has quit IRC19:47
vzcxi appreciate the effort at least! zipcpu is very cool and having it as an example is really accelerating my practical knowledge of comp arch and verilog19:49
ZipCPUMy own knowledge of FTDI+USB is really slim as well19:50
*** dys has joined #yosys20:01
*** seldridge has quit IRC20:07
*** seldridge has joined #yosys20:14
corecodedaveshah: how do i find where PLLOUT_B is located at?20:32
corecodei guess it is PLLOUTCORE[1]20:32
corecodebut i'm looking at a vlog output, and i can't identify the location20:32
daveshahit will appear as an "input pin"20:32
corecodethere is a whole lot of routing20:33
daveshahyou should see a D_IN_0 in there?20:33
corecodebut where do i find the , 0 or , 120:33
corecode// (13, 21, 'io_0/D_IN_0')20:33
corecodefrom the io_0?20:34
daveshahthe PLLs are in the  input path20:34
corecodesorting the routing information by coordinate is not as useful as sorting it by connection20:34
corecodeshould i run a connectivity test?20:35
daveshahyes, that would be a good idea20:36
corecodeit took very long last time, and then i aborted20:36
corecodeyou had some feedback on not using the 8k ram db or something like it20:37
daveshahyeah, you should be using the 8k ram db not the 1k ram db20:37
corecodei thought i was20:38
corecode            elif self.device == "5k" or self.device == "u4k":20:38
corecode                add_seed_segments(idx, tile, rambtile_8k_db)20:38
daveshahthat looks good20:38
corecodethen it must have been something else20:38
daveshahthe problem was in the icefuzz makefile I think20:38
corecodei guess that makefile needs some work20:41
corecodedo i need to build my own u4k bitdata_dsp?20:42
daveshahHave you seen any changes to the dsp bitdata?20:43
corecodethis one special dsp bit that lives elsewhere doesn't exist for me20:43
corecodeor rather, is uniform like the other dsps20:43
corecodei don't think i quite understand this bitdata thing20:44
daveshahThe lack of a special bit doesn't matter, that's all dealt with in icebox20:45
daveshahthe bitdata contains the routing bits, and low-level names of config bits20:45
daveshahhigher-level mapping is done in icebox20:45
*** SpaceCoaster has quit IRC20:53
*** SpaceCoaster has joined #yosys20:55
*** seldridge has quit IRC21:42
sxpertcorecode: you guys are hacking at yet another ice40 ?21:43
sxpertcrap, more work: DEC_INIT 2: nibble 9 not handled21:44
*** dys has quit IRC21:57
*** dys has joined #yosys22:05
corecodewhat's that error message?22:30
corecodeyea, ice5lp, aka ice40 ultra22:31
*** vzcx has quit IRC23:05
corecodeModule SB_RGB_IP is not a valid primitive. Please check23:14
emebcorecode: glad to hear you're doing ultra!23:15
emebI've got a large stash of ice5lp4k sg48 parts leftover from a while ago.23:16
emeb(and I know someone who has a whole reel of them that he's probably never going to use)23:17
corecodei'll take them :)23:17
daveshahcorecode: oh lmao23:17
daveshahI remember reading about this23:18
daveshahthe hard SB_LEDD_IP primitive in the ice40 ultra is broken23:18
daveshahSB_RGB_IP isn't a primitive at all, just soft logic23:18
emebI thought that was just the PWM stuff that was borken23:19
emebbut the actual high current drivers work OK23:19
daveshahyeah, that is SB_LEDD_IP/SB_RGB_IP23:19
daveshahthe drivers are indeed fine23:19
emebyeah - I've run into that too.23:19
corecodeah what23:19
corecodeso do i skip that?23:20
emebprobably best23:20
emebunless you want to make a synthesizable soft core for it :)23:21
corecodeso what is broken?23:23
corecodei can't find documentation on the SB_LEDD_IP23:24
daveshahno, because it is broken23:25
corecodebroken how?23:28
corecodeit was supposed to do some driving?23:28
corecodeor is that the pwm ramp generator23:28
daveshahit's a pwm generator core (for things like fading/ breathing effects), it doesn't do the actual high current stuff23:28
emebcorecode: you in the US?23:30
corecodeemeb: no23:30
corecodeok the icefuzz makefile runs23:30
daveshahdo you see any changes to icebox/iceboxdb.py once it has finished running?23:31
daveshahgood, that means low level bits are the same23:32
corecodewell, over all, yes23:32
corecodeso now i can run the23:32
tpbTitle: Comparing cliffordwolf:master...corecode:u4k · cliffordwolf/icestorm · GitHub (at github.com)23:32
corecodethere are some changes, but they seem unrelated?23:32
corecodei don't know where these come from23:32
daveshahthose are because of the ram database issue23:33
daveshaheffectively you've put the 8k/u4k/all newer ice40 ram bits into the 1k db23:33
corecodewhy doesn't it get fixed?23:33
corecodeah, i need to run the generation for the 1k again23:33
daveshahno, the database is accumulative23:34
corecodeor rather, i revert to the original state, and then run for the u4k23:34
daveshahyou'll need to checkout iceboxdb.py from master and run again23:34

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!