Monday, 2019-02-18

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MoeIcenowysxpert: I think someone did initial RE on EP4CE602:18
MoeIcenowyBTW I have ordered a EP4CE115 board for CNY ¥495 (around USD $75)02:20
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promachis it possible that bmc passed at depth = 5 , but failed at depth = 10 ? Note that I am using "proof: depth 10" in sby file08:10
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ZipCPUpromach: Absolutely!10:07
ZipCPUIt's actually a common problem in one of my counter exercises.  The counter gets set and starts counting down from 22, goes to idle, and then gets set and counts down again10:08
ZipCPUThe only problem is ... we use a depth of 20 for the exercise, and there are often bugs at the point where the counter stops, waits, and restarts -- all at clock 22+, long after the 20 clocks necessary for the depth of 2010:09
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promachZipCPU: ok11:00
promachI know what went wrong in my code now11:00
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corecodewhat did?11:37
corecodedaveshah: how should i proceed with this port?11:37
daveshahcorecode: have you tested some small designs through icebox_vlog11:38
corecodenot explicitly11:40
corecodei think some of the test scripts do that11:40
daveshahIt would be worth trying a few designs manually and making sure the output is sane11:41
corecodei think at least i need to confirm the global networks & pins11:43
daveshahThere are some Verilog designs for testing global networks in icefuzz/tests11:44
corecodeyea, i will have to add some other footprint to cover all pads11:45
daveshahIf it's anything like the UltraPlus, not every theoretical pad is covered even over all footprints...11:45
corecodewhat does that mean11:46
daveshahthere are some IO locations that are not used in any package11:46
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MoeIcenowymaybe they will furtherly provide packages with more pins ;-)12:24
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corecodedaveshah: hm, the ultralite datasheet says that global pin X is connected to global buffer X22:42
corecodeis that different from global network X?22:42
daveshahNo, it isn't22:42
daveshahglobal pin X drives global buffer X22:43
daveshahalso, are you doing the ultra or the ultralite, btw?22:43
daveshahbeware that the SB_GB which drives from fabric (as opposed to SB_GB_IO from the global pin) at the same location drives a different global network22:44
corecodeultralite, i think ice5lp22:44
daveshahice5lp isn't the ultralite, it's the ultra22:44
corecodewhy are they so bad with names22:45
daveshahthe patch so far was the u4k, which is the ice5lp/ultra not the ultralite22:45
daveshahyeah, ikr22:45
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corecodedaveshah: how would i force use of a specific global network?  i'm trying to figure out the fabout locations23:24
daveshahcorecode: you can constrain it in the icecube floorplan view, or in the pcf file23:24
daveshahI can't remember the syntax for the latter23:24
corecodei'll just skip the two padin that don't exist on this footprint23:25
daveshahicebox requires all 8 padins23:26
corecodebut there are not even 823:26
corecodeat least not documented23:26
daveshahthe remaining ones should be at the same location as the fabouts23:27
corecodeand what about the extra bits?23:27
corecodejust keep them short?23:27
daveshahmissing extra bits are fine23:27
corecodethank you23:27
daveshahit's only the padin_pio db that has to have 8 entries23:27
daveshahtwo of the extra bits will come from the oscillators23:28
corecodeah i guess it is called gbufin23:28
daveshahhopefully with oscillators and all packages all 8 extra bits will be covered in any case23:28
corecodei don't think so23:28
daveshahgbufin is the fabouts (x, y, global network)23:29
corecodebit of a misnomer23:30
daveshahfor some reason the documentation for it ended up in (the exporter)23:31
tpbTitle: icestorm/ at master · cliffordwolf/icestorm · GitHub (at

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