Saturday, 2019-02-16

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emebcorecode: what are you doing?00:03
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corecodeemeb: actually i just want to try my forth cpu on an fpga00:59
corecodebut icecube2 fails to place it01:00
corecodeso now i'm - under protest - porting icestorm to the fpga i'm using01:00
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emebcorecode: interesting problem04:14
emebwhich FPGA are you using?04:14
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corecodethe ice5lp1k10:17
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sxpertdaveshah: getting some messages from yosys when compiling about "assert" being used while read_verilog is not called with -sv on ecp5/cells_sim.v:41[1-4]10:19
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mrecI wonder is Clifford here?11:31
daveshahsxpert: hmm, perhaps an ifdef is needed11:37
daveshahmrec: no, not usually11:37
mrecsome of his slides seem to be wrong ice40up5k doesn't have 128kbit bram, it's supposed to be 120kbit11:38
daveshahIndeed that is correct, I'll let him know11:38
daveshahThe lp8k/hx8k does have 128kbit11:39
mrecwell the specs are also wrong at the bottom of the pdf11:39
* sxpert would like an ECP-5 100k with 8Mbit of bram ;)11:41
mrecI'm happy with the ice40up for small items, the crappy linux spi implementation needs a lot cache11:42
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daveshahSPRAM would probably make sense11:44
mrechmm is there anything better/faster/free available for simulating ice40 (mixed vhdl/verilog) designs than ActiveHDL?11:46
daveshahMixed HDL, probably not11:48
mrecit takes quite a few seconds to simulate 10 milliseconds11:49
mrecmore like a minute+11:49
daveshahVerilator will be much faster, but is Verilog only11:49
daveshahit also might not support the vendor verilog models, because it doesn't implement the full event model, but it should work with the Yosys ones11:50
corecodei have no idea whether i am 10% or 90% done with the ul port11:52
daveshahIf you want to create a PR or stick the repo somewhere I'm happy to take a look11:54
daveshahIf you can get meaningful output from icebox_vlog for a few small designs from icecube (unpacked with iceunpack) then that's a good first step11:56
* sxpert is happy, his decoder and alu can both be stalled at the same time by the bus controller11:56
sxpertfor example, when said bus controller will have to go fetch some dram data11:57
tpbTitle: Comparing cliffordwolf:master...corecode:u4k · cliffordwolf/icestorm · GitHub (at
corecodesome stupid whitespace changes in there as well - auto whitespace cleanup on save12:06
daveshahcorecode: mostly looks good. Main comment right now is that the "_8k" RAM databases should be used, not the unprefixed (1k) ones12:18
daveshahThe icebox changes all make sense12:20
corecodeyea it's just that several of the icebox changes are not tested, just copied from the 5k12:45
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promach_ZipCPU sxpert : had passed bmc, induction and cover()16:18
tpbTitle: A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm · GitHub (at
promach_and this multiplier code had also no problem with A_WIDTH != B_WIDTH so far16:20
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promach_strange, when A_WIDTH = B_WIDTH = 4 , induction passed,   but induction failed when A_WIDTH = B_WIDTH = 616:27
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corecodewhat is this sby file?17:04
daveshahsby is the config file for SymbiYosys, a wrapper around Yosys and various SAT/SMT solvers for formal verification17:05
corecodeah, thanks17:19
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