Thursday, 2019-02-14

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promach_ZipCPU: Which part of the code you still do not understand ? I will make them clearer01:18
corecodedaveshah: do you know how the colbuf_db is made?01:21
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corecodei made + ran a colbuf_io*.sh, but i don't know what i am looking for in the output01:21
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corecodeyea i need some assistance figuring out these last bits02:38
corecodeunclear where they come from and what the order needs to be02:39
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daveshahcorecode: colbuf_logic is probably the most important script.08:48
daveshahYou should get four numbers per line08:49
daveshahin each case, x and y of the column buffer and x and y of the global user08:49
daveshahChances are that x will be the same for both08:49
daveshahSo then in you are creating a mapping from global user location (the second pair of numbers) to colbuf location (the first pair)08:51
daveshahI think there is also a script to visualise this as an svg08:51
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corecodethe script falls on its face tho, because it icebox to already know where the colbuf is10:46
corecodei think10:46
daveshahNo, it only needs to know what the colbuf bits are11:03
daveshahThey should be the same across devices11:03
daveshahThat's different to the tile locations where colbufs are11:04
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promachZipCPU: Which part of the code you still do not understand ? I will make them clearer. I need your comment because that would make the code more user-readable and user-friendly11:49
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sxpertthere is $display, is there a $waitkey function ?14:12
ZipCPUWhen using Verilator, it's not that hard to build.  As I recall, that was one of my tutorial lessons ;)14:13
sxpertZipCPU: so I rewrote it all again ;)14:43
sxpertyosys finds 669 cells and next-pnr finds 316, is that supposed to be normal ?14:46
sxpert(after all there's 2 lut per cell, so that seems plausible)14:46
ZipCPUsxpert: Yes, that's normal14:46
sxpertso far, I manage to execute the first 8 instructions of the rom ;)14:47
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somlodaveshah: after prjtrellis commit 72418c7 there's still an explicit basecfg reference in examples/picorv32_versa5g/Makefile; do you want to fix that separately, or should I include it in the rebased PR #59 (where I'm adding "TRELLIS=/usr/share/trellis" to get rid of the remaining openocd relative paths?17:11
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tntcorecode: mm, what are you working on if you don't mind me asking ?17:19
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corecodetrying to get ice5lp support in icestorm17:25
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tntcorecode: ah, nice ! I thought that might have been it from the questions, but wanted to double-check :p17:29
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daveshahsomlo: feel free to add to your PR18:02
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somlodaveshah: done18:10
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keesjwhat is the story with anlogic are they open to providing information?20:03
tpbTitle: Sipeed TANG PriMER FPGA Development Board - Seeed Studio (at
daveshahmicko is working on them:
tpbTitle: GitHub - mmicko/prjtang: Documenting the Anlogic FPGA bit-stream format. (at
keesjthanks daveshah I just found it !20:08
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