Monday, 2019-02-11

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promachCould anyone comment on ?03:39
tpbTitle: 3D array bitwidth mismatch : yosys (at
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chaseemoryi imagine its some confusion with packed vs unpacked arrays, in your case mixing both, but the output should be 8bits no?04:15
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emeb_macdoes there exist a library of stubs for the Lattice SB_* cells that can be used for linting w/ Verilator?05:29
emeb_macor is there some way to blackbox those w/o a library?05:30
promachchaseemory : if you look at , I am using "Unpacked Array Assignment"05:31
tpbTitle: SystemVerilog Arrays, Flexible and Synthesizable - Verilog Pro (at
promachreg [(A_WIDTH+B_WIDTH-1):0] middle_layers[(NUM_OF_INTERMEDIATE_LAYERS-1):0][0:(SMALLER_WIDTH-1)];05:36
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daveshahemeb_mac: might do the trick07:55
tpbTitle: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at
promachis it true that yosys does not support packed array yet ?  logic [A-1:0][B-1:0][C-1:0] array;08:04
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sxperthow would I <= the same value to multiple things at the same time ?09:41
sxpertdo I have to copy / paste the operation, or is there a nicer way to do that ?09:41
daveshahIf the destination is an array, then use a for loop09:57
sxpertno, it's like I calculate some value, and needs it in 2 reg10:01
sxpertwhich are used by 2 different things10:01
sxpertsay, the alu_dest register and the dbg_dest register10:02
daveshahThis is a rare case where non-blocking assignments are reasonable10:04
daveshahe.g tmp_result = op; alu_dest <= tmp_result; dbg_dest <= tmp_result10:05
sxperthowever verilator would somehow complain I guess10:05
sxpertdaveshah: can tmp_result be declared locally ?10:06
daveshahNot in traditional Verilog, SystemVerilog probably supports something like that10:07
sxpertI see10:07
daveshahEither way it is essential that tmp_result is only accessed and written in one always block10:07
daveshahotherwise it might be a race condition in simulation10:07
sxpertI suppose reading from multiple locations would not be a biggie10:08
daveshahThis is definitely where VHDL wins, the "variable" local to a process is much nicer10:08
sxpertI see10:08
daveshahsxpert: multiple locations in one always block is fine10:08
daveshahIn different always blocks there are race condition issues in simulation10:08
sxpertI see10:08
sxpertunlike with <=10:08
daveshahThis is one reason why = is generally discouraged10:09
daveshahin clocked always blocks10:09
daveshahTemporary results are a limited exception10:10
sxpertthe fact that the concept of temporary results are missing from the language is an oversight IMHO10:10
daveshahYes, just checked and it is fixed in SystemVerilog, a reg can be inside an always10:12
sxperthave a link ?10:12
tpbTitle: Can Verilog variables be given local scope to an always block? - Stack Overflow (at
daveshahYosys only supports this if the block is named10:16
daveshahie you have :somename after begin10:17
sxpertI see10:17
sxpertcome to think of it, it seems that there are a few combinations in the opcodes, so I could make a few wires ...10:17
sxpertand reuse them elsewhere10:18
sxpertshould generate less logic overall, I guess10:18
daveshahMaybe, but many of these cases will be dealt with by opt_merge10:19
sxpertwill make it nicer to read too ;)10:20
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AnkurAHey all, not able to do synthesis with .plib provided by foundry10:51
AnkurAany idea if .plib cannot be used?10:51
daveshahYosys supports Liberty libraries for ASIC synthesis, is that what a .plib is?10:52
AnkurAany other ways to do it if the foundry has not provided .lib liberty file?11:03
AnkurA.plib is some physical library file11:03
AnkurAexcepth, various other files are provided like .db, .sef, .nldm, etc.11:05
AnkurAexcept .lib I meant11:05
daveshahMany of these files are proprietary11:10
daveshahIt looks like the plib might be a heavily extended Liberty, in which case it might be possible to modify Yosys to skip over the bits it can't use11:11
AnkurAFound .lib in nldm folder11:15
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sxpertdaveshah: soon there will be an opensource library for opensource asics with opensource process, I understand12:25
sxpertthat looks pretty interesting12:26
daveshahother than the blockchain stuff12:26
sxpertwhat blockchain stuff ?12:27
daveshah> By using a blockchain solution in order to track the added value from the work of every contributor, without any human intervention required, it is ensured that everyone is being payed a fair price for the work and time she or he has invested into developing an ASIC or IP block. Manufacturing potential can be reported on a market place where customers can put up orders. The result will be something like a crypto exchange12:27
daveshahjust without speculation, a way for people who want to buy chips and people with a basement containing a clean room to find each other. This becomes possible with our free semiconductor manufacturing process standard which allow reproducible results with varying setups.12:27
sxpertnot really interested by that part12:28
sxpertthe silicon manufacturing bit is the important part here12:28
sxpertguess they needed "Blockchain" somewhere in the blurb to get financing12:28
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corecodelol blockchain12:58
sxpertit's one of those magic buzzwords to get money from know-nothing capitalists. can be considered as a nop13:33
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cr1901_moderndaveshah: Do you have a moment to hear about our lord and savior blockchain?14:08
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somlo"If you think blockchain is the solution to your problem, you don't understand blockchain. And, you don't understand the problem"14:18
sxpertI think I'm getting somewhere14:53
sxpertguess I should be splitting this ALU thing with the registers into a separate module14:53
sxpertwill try that later14:54
sxpertfeels like major surgery though14:56
sxpertdaveshah: what does "Clock '$glbnet$ph1' has no interior paths" means ?15:15
daveshahThat means there are no paths between two registers both clocked by ph115:17
daveshahTherefore a Fmax is not applicable15:17
daveshahhowever, max delays to/from other clock domains may be printed15:18
sxpertis that a problem ?15:19
daveshahProbably not15:20
daveshahAre you expecting all the registers clocked by ph1 to drive and be driven by registers in other domains?15:21
sxpertI'm actually trying to isolate things into their own domain15:22
sxpertone at a time15:22
daveshahThat sounds dangerous15:22
sxperthmm ?15:22
daveshahGood practice is to have as few clock domains as possible15:23
daveshahIn many cases, everything except IO belongs in a single design15:23
sxpertwell, ph[0-3] are derived from a common clk15:24
sxpertwith this :
tpbTitle: hp-saturn/saturn_core.v at master · sxpert/hp-saturn · GitHub (at
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daveshahFPGA logic is not glitch free15:26
daveshahThis could end up with double clocking issues15:26
sxperthow should I do that then ? ;)15:28
daveshahFirst of all you shouldn't15:29
sxpertwell. duh15:30
daveshahIf you really have to then a PLL is the only safe way to generate related clocks15:30
sxpertI see15:30
daveshahRegisters will be better than combinational logic, but still far from ideal15:30
sxpertsay I could use some form of counter ?15:30
sxpertok, works for me.15:32
sxpertwill redo that part15:32
sxpertso, one clock, and a 2 bit counter for phase15:35
sxpertworks for me15:38
* ZipCPU takes a look at sxpert's saturn_core clocking logic15:46
ZipCPUsxpert: +1 to everything daveshah said.  Consider this post if you want further reading:
tpbTitle: Controlling Timing within an FPGA (at
* sxpert obviously does all the beginner's mistakes ;-)15:49
sxpert(that's part of learning, I guess)15:49
ZipCPUAs long as its the fun part of learning, have at it!15:49
sxperthaving a blast15:51
ZipCPUYou realize I'm only a couple of years ahead of you, right?  ;)15:55
sxpertZipCPU: so I need to pass clk and counter to the modules IIUC15:55
sxpertZipCPU: good enough, I'm a couple years behind ;)15:55
ZipCPUI would instead pass a clock and an enable line, with four enable lines--one per phase15:55
ZipCPUThat'll reduce the amount of logic required to use the phase15:56
ZipCPU... and, if you are on an iCE40, you'll need all the reductions you can get15:56
sxpertso, generate those enable on neg-edge15:56
sxpertand use then on posedge ?15:57
sxpert(which allows the enable to be stable when posedge comes up15:58
ZipCPUNo.  Do everything on the positive edge15:58
ZipCPUMost toolchains can't handle both edges of the clock15:59
ZipCPUPart of the problem being that few clocks are sufficiently reliable on both edges too15:59
sxpertthis is what I understand will happen :
tpbTitle: hp-saturn/README at master · sxpert/hp-saturn · GitHub (at
ZipCPULooks good16:06
sxperthowever, on posedge, the phase will not be stable16:07
sxpertor is the logic happening before the clock edge ?16:08
sxpertZipCPU: link above is most enlightening16:18
ZipCPUYou mean the one I wrote?16:18
sxpertstill, I'm puzzled by how this all works16:19
ZipCPUHow so?16:19
sxpertall the logic described in the "always @(posedge clk)" block, is combinatorial logic and the clk controls all the touched flip-flops ?16:20
ZipCPUI'm not sure I follow yet16:20
sxpertI mean, that's how the fpga works inside ?16:20
ZipCPUInternal to an FPGA are LUTs, FFs, and wires to connect them all16:21
ZipCPUMany FPGAs group the LUTs and FFs together into logic blocks16:21
sxpertso what's inside the block is a bunch of luts, and the ff store whatever the luts have generated on the clk (up or down) signal16:22
ZipCPUThe LUTs are your combinatorial logic, and are (often) immediately followed by FFs.  The FF in the logic block can be bypassed, though, if you aren't interesteed in using it16:22
ZipCPUYeah, something like that16:22
ZipCPUIn addition, most FPGAs have some low-latency networks for clocks to help reduce clock skew from one part of the chip to another16:22
ZipCPUThese low-latency networks, which are limited in number, tend to be fed to every logic block16:23
sxpertyeah, I had that part in the brain ;)16:23
ZipCPUThe other part of the FF thing is that many FFs have CEs built into them16:23
ZipCPUHence, your phase signals (once created) should be able to use the global routing networks, and then no additional logic at the FF16:23
sxpertI see16:23
ZipCPUUnless Yosys adds some more combinational logic, such as the FF only changes if A & B are true16:24
sxpertsaid phase signals should be "wire blah; assign blah = <something>;" ?16:24
sxpertthe something being a function of counter16:25
ZipCPUWell, you could say: wire [3:0] phase_ce; assign phase_ce[0] = counter[1:0] == 2'b00;16:25
ZipCPUDid you see my explanation of timing in terms of stalagtites and stalagmites16:26
ZipCPUIt was on pages 10-13 of the tutorial lesson on debouncing (lesson 7) ... see
tpbTitle: Verilog Beginner's Tutorial (at
ZipCPUIf you use wire [3:0] phase_ce; assign phase_ce[0] = (counter[1:0] == 2'b00); your starting your design out in timing debt, and won't be able to do as much on the clock16:27
ZipCPUOn the other hand, if you use: reg [3:0] phase_ce; always @(posedge i_clk) phase_ce[0] <= (counter[1:0] == 2'b00); your phase will be delayed by one clock tick (probably irrelevant) but you'll have more time to get things done based upon that value within your design16:28
sxpertah. I see16:28
sxpertas long as the thing starts with phase_0 on reset16:29
ZipCPUThat should be easy to verify16:29
sxpertanother Q I had was, is a monster case statement bad for timing ?16:30
ZipCPUIt can be16:30
ZipCPUIt isn't necessarily so though16:30
sxpertany known red-flags ?16:31
ZipCPUYou mean with the monster case statement?16:31
ZipCPUSome designs/designers use them often.  I don't.  Here's why ...16:31
ZipCPUThe larger the case statement is, or the nested if, whatever, the more logic is required to compute every value16:31
ZipCPUMy own design philosophy has always been about minimizing my logic usage count--hence the ZipCPU16:32
ZipCPUThat usually forces me to move every register's definition/assignment into its own always block16:32
ZipCPUHave you seen my article on minimizing logic utilization?16:33
sxpertyeah, but guess I'll have to read again16:33
ZipCPUA lot of what I do is optimizing logic for those time periods where I don't care what a particular value is16:34
ZipCPUAnother big part of what I do is to work very hard to minimize the logic used when that logic needs to be applied to lots of values16:35
ZipCPUFor example, if (A) WORD <= I1 + I2; else if (B) WORD <= I1 ^ I2; else if ...16:36
ZipCPUSometimes you can't get around it, like when building an ALU, but sometimes you can16:36
sxpertwell, the ALU I built works in multiple phases, minimizing the work in each phase16:40
sxpertph1: get the data, ph2: do calculation, ph3: write back16:41
ZipCPUWhat if the calculation takes longer?  Such as a multiply or a divide?16:41
sxpertph0 being request data from memory16:41
sxpertthere's no such instruction ;)16:41
ZipCPUAre you only ever using block RAM?  Never any flash memory?16:42
sxpertnot at this time16:42
sxpertI was thinking of plugging some form of cache though, that would stall the processor while it accesses said flash on PC changes16:43
sxpertas I understand, flash works in a streaming fashion, as long as you request the next value16:44
ZipCPUYou are working on an ECP5, right?  I could never get the cache to fit on an iCE4016:44
sxpertthe original processor was 4Mhz...16:44
sxpertZipCPU: how much cache were you trying to have ?16:45
ZipCPUI stripped it bare, down to two cache lines of 8 items each--still too much logic16:46
sxperthow big was that ice40 ?16:47
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sxpertso that's 8k luts ?16:53
ZipCPU7680 if I recall, but roughly 8k, yes16:54
ZipCPUThey're 4-LUTs too, as opposed to the Xilinx 8-LUTs16:54
sxpertnot much indeed16:54
ZipCPU(I'm not sure how big the LUTs are on the ECP5)16:54
sxpertI can see how that gets filled up pretty fast16:55
daveshahLUT4s, but with cascade muxes to combine to build larger LUTs16:55
daveshahXilinx is LUT6 btw16:55
ZipCPUThanks, daveshah!16:55
daveshahbut also has muxes to build larger LUTs like ECP516:55
ZipCPUOohh, thanks, Looks like I mistyped that as 8-LUTs for the Xilinx chips, my bad16:55
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sxpertZipCPU: 1 slice is 2 LUT4 and 2 FF16:57
ZipCPUdaveshah would know that better than I.  Are you asking regarding iCE40 or ECP5?16:58
daveshahsxpert: yes16:58
sxpertreading from the datasheet16:58
sxpertthose lut4 have carry in and out too16:58
daveshahYes, there's some carry logic in there16:59
sxpertdoesn't say how many outputs those luts have though17:00
daveshahin carry mode it's a bit more complicated17:01
sxpertso that's a 1 bit adder or something17:01
daveshahit can be drawn like this in most cases17:03
daveshaheffectively the LUT2 is the bottom half of the LUT417:03
daveshahalthough they can have separate init values if you treat the top part as a LUT3 and tie the D input to 117:03
sxpertso that uses 2 luts ?17:05
daveshahno, those are both parts of the LUT417:05
sxpertah ok17:06
sxpertthe lut4 is thus built with 2 lut3 internally ?17:08
daveshahIt's really a LUT4 with the output from the bottom LUT2 broken out17:09
daveshahbut in almost all cases the remainder is used as a LUT317:09
daveshahin the carry situation17:09
* sxpert wonders how there's 2 outputs ;-)17:10
daveshahall  a LUT is is a cascade of multiplexers17:10
daveshahselecting one of 2^K config bits17:10
daveshahto get the second "LUT2" output, you just need to tap off from the middle17:10
daveshahhowever, this second output is only used as part of the carry logic, it's not generally usable17:11
sxpertah, I thought it was some sort of 2^K bits ram17:11
daveshahit is17:11
daveshahindeed, 4 out of the 8 LUTs in a tile are usable as ram as well as rom17:11
sxpertI was thinking of the config bits here17:12
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sxpertsay you have a 4-16 mux selecting which of the 16 config bits come out the output17:13
sxpertand then next to that, you have a ff that you can clock whatever comes out into17:14
daveshahfor LUTs not usable as distributed RAM, it will be probably be a simple shift register17:15
sxpertthe part I don't get is how you get a 2nd input as the cout (the c-in is just one of the 4 input bits)17:15
sxpertperhaps you have a second 3-8 mux selecting one of bits [8-15]17:16
daveshahthe mux connecting cin/cout isn't one of those muxes, that's an extra carry mux17:16
daveshahsee this badly edited stolen diagram17:19
sxpertoh, I see... this is much more clear17:20
sxpertimho, would have been smarter to have the possibility of splitting into 2 lut317:20
daveshahyeah, but then you hit routing fabric constraints17:21
sxpertis there a doc from lattice with this sort of info ? or does this comes from somewhere else ?17:21
daveshahit came from careful analysis of their simulation models (see $DIAMOND/cae_library/simulation/verilog/ecp5y)17:22
daveshah* $DIAMOND/cae_library/simulation/verilog/ecp5u17:22
sxpertah, bloody RPM ;)17:24
sxpertah, and one needs an account...17:24
daveshahFeel free to peruse the rewritten FOSS alternatives17:25
tpbTitle: yosys/cells_sim.v at master · YosysHQ/yosys · GitHub (at
daveshahis the model for the CCU2C carry primitive17:25
* sxpert bookmarks17:27
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emebTrying to run a design thru nextpnr-ice40 and it fails with "ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc."17:46
daveshahemeb: could it be an inferred latch? try grepping the Yosys output for dlatch17:47
emebdaveshah: thx - will look.17:48
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emebdaveshah: found a few latches inferred in yosys - easily fixed w/ fully specified case. That did not eliminate the ERROR though.17:59
daveshahIs it possible there are other forms of combinational loop in there?18:01
daveshahIf you just want to get rid of the error, run nextpnr with --ignore-loops18:01
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emebdaveshah: it's possible - I'm using a 6502 IP core of unknown quality.18:03
daveshahIn that case --ignore-loops is your best bet18:05
emebYes - thanks. that seems to let it run further, exposing some other interesting things to chase.18:07
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sxpertZipCPU: does this look good ? ?18:33
tpbTitle: hp-saturn/saturn_core.v at master · sxpert/hp-saturn · GitHub (at
ZipCPUsxpert: Not yet18:38
ZipCPUWhat do you intend to do on a reset?18:38
ZipCPUYou've only covered one half of the reset case18:38
emebdaveshah: also - thanks for the link to the SB_ lib yesterday. just read the chl log and spotted that.18:46
emebwhich raises another question - is yosys able to infer the SB_SPRAM256KA ?18:47
daveshahNo, it isn't18:47
daveshahatm Yosys doesn't support shared read/write ports of any kind18:47
sxpertZipCPU: how would I go for that reset thing ?18:47
daveshahthis also means it can't infer Xilinx/ECP5 true dual port RAM, only pseudo dual port (1R1W)18:47
sxpertZipCPU: for now I expected to use the initial block, but that may not be the best solution18:48
ZipCPUsxpert: You want a structure such as: initial A <= 1'b0; always @(posedge i_clk) if (i_reset) A<= 1'b0; else A <= !A;18:48
emebdaveshah: OK, that makes sense. I was having trouble with inference so I just instantiated.18:48
sxpertZipCPU: so as to debounce the reset ?18:49
sxpertor to buffer it somehow ?18:49
emebdaveshah: and I was able to get my whacky 6502 thing to build - found a loop, broke it, now everyone is happy.18:49
ZipCPUTo set your values both on a reset as well as following the reset18:49
emebpro-tip - yosys does check for loops and warn about them. TIL. :P18:50
sxpertZipCPU: what would A be used for ?18:51
sxpertinitial does only apply on fpga bootup...18:51
sxpertI see18:51
ZipCPUI'm using A to avoid retyping all 9 of your assignments18:51
sxpertyeah right18:51
sxpertwhy !A though ?18:53
ZipCPUTo avoid saying: clk_phase <= clk_phase + 1;18:53
sxpertshould ah18:53
ZipCPUI was just trying to share the form of the solution18:53
sxpertand reset all other signals to 018:53
sxpertI guess18:53
ZipCPUWell ... that's not quite a given18:54
ZipCPUThe issue is that you want all of the en_* signals set to zero during the reset, and you then want en_bus_send set on the first clock after the reset18:55
ZipCPU(That was your requirement, not mine)18:55
sxpertah right18:55
sxpertguess I can lose a step18:56
sxpertnot a biggie18:56
sxpertso all to 0 would work18:56
sxpertok, I have created a delayed reset enable too19:09
sxpertZipCPU: yay, seems to work ;)19:23
sxpertnow, I need to figure out the rest ;)19:23
sxpertthere, removed all the old stuff (stored in a safe place)19:34
sxpertZipCPU: the "generate if(blah)" is for optional stuff that may not get compiled in ?19:42
ZipCPUI use it for that purpose, yes19:42
ZipCPUblah must be a 1'bit parameter to make it work19:42
sxpertok, won't need that ;)19:43
ZipCPUI suppose you could make it a localparam too ...19:44
sxpertor some `define19:47
ZipCPUI've had problems using `define's over the years19:49
ZipCPUI've used them on many projects19:50
ZipCPUThe result usually ends up with something that's less capable, since it's harder to handle `define's in these projects19:50
sxpertI see19:58
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sxpertZipCPU: here's what I came with,
tpbTitle: hp-saturn/saturn-decoder.v at master · sxpert/hp-saturn · GitHub (at
ZipCPUsxpert: What am I looking at?20:46
sxpertwell, trying to apply whatever I learned tonight, dunno if I did well20:48
sxperton i_en_dec, it receives 0, then 0, ends up setting the ins_rtnsxm reg to 120:50
sxpertone of the questions I had was respective to mucking with continue on line 59 and 7820:51
ZipCPUStill not following what I'm looking at.  Does it do what you want it to?20:53
sxpertsimulation says so20:53
sxpertI'm just trying to ascertain that it's synthesizable20:53
sxpertand proper ;)20:56
sxpert(before I start coding the rest of the decoder in the same fashion20:56
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ZipCPUIt's not synthesizable21:17
ZipCPUNeither $display nor $monitor can be synthesized ;)21:18
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sxpertok, not doing what I want, YET21:30
ZipCPUYou know .... it's a whole lot easier to get that sort of thing working with formal methods than with simulation ... just sayin'21:30
* sxpert wonders wth are those formal methods21:31
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* sxpert got it to work !21:35
chaseemoryTIL you can concat wires with an enum in a case block21:48
sxperthmm ?21:49
chaseemoryid been curious for a while if it would work, i wrote this21:50
chaseemorycasex( {current, send_i, hdr_ready_i, payload_axis_tready_i} )21:50
sxpertyeah, seems to work21:50
sxpertgenerates some bitstring you can compare against21:50
chaseemorywhere current is an enum, and the rest are wires, and just concatted them together for each case as well21:50
sxpertsuppose it allows for testing all cases of the enum ?21:51
chaseemorycould even test the same cases of the enum with different combinations of the wires as well, its being used in my next state logic block21:54
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sxpertgood luck with that ;)22:04
chaseemoryhehe I like trying to new things to see how they work :D22:18
sxpertsometimes, they fail spectacularly for no reason22:34
chaseemorydont I know it, now that Ive gotten into ASIC toolchains in school vs just FPGA ones till now, they can go belly up quick and in strange ways23:19
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