Sunday, 2019-02-10

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promach_ZipCPU: voodoo ?02:48
promach_it seems like the cover(in_valid) failure got to do with    initial assert()03:02
promach_but I do not know why exactly this leads to cover() failure03:03
promach_ZipCPU03:03
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maikmertenmost surprising thing I found out in the last 24 hours: This does [email protected] VGA without glitching: https://pasteboard.co/I0vtcVD.jpg11:47
tpbTitle: Pasteboard - Uploaded Image (at pasteboard.co)11:47
maikmertenI certainly would not have assumed that one can somehow drive a ~147 MHz pixel clock through such a setup, without any attempt of termination etc.11:48
maikmertenso the signals signals go FPGA board -> extension board with SRAM and Pmod -> Pmod connector -> Pmod to ISP cable adapter -> ISP cable -> ISP cable to Pmod adapter -> Pmod connector -> non-inverting bus driver with resistor DAC11:51
sxpertworks as long as your total wire lengh < 1m or so12:05
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maikmerten"<sxpert> works as long as your total wire lengh < 1m or so" -- that sounds like a very thumby rule of thumb ;-)14:00
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corecodehi15:11
corecodei guess in the end i do have to port icestorm to my ice5lp, because icecube's placer fails with my design15:12
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sxpertmaikmerten: it is ;)15:15
sxpertcan I use "=" for a result that I need in a calculation immediately in an "always @(posedge clk)" block ?15:17
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maikmertensxpert, yes, I'm pretty sure I used that once15:41
maikmertensxpert, ended up removing that, though, because verilator does *not* allow that15:42
maikmerten(iverilog is okay with that style, though)15:42
maikmertenokay, yes, used that a while back15:43
maikmerten always @(negedge clk) begin15:43
maikmerten ...15:43
maikmerten if(!busy) state = nextstate; // assume new state NOW!15:43
maikmerten...15:43
maikmerten  case(state)15:43
maikmertenetc. etc.15:44
maikmertenI *think* that style isn't overly recommended, though15:45
maikmertenfor reasons more experienced Verilog developers can surely elaborate on ;-)15:45
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corecodesounds you're mixing combinational logic and flops?16:23
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sxpertok so it's frowned upon16:44
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corecodei'm by no means an expert, but separating (complex) combinational logic and clocked logic (flops) helps understand the design better17:22
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lutsaboundsxpert: why not use an @* block instead?17:34
somlo_daveshah: nextpnr PR #219 took me from 4:49:42 down to 0:17:26 (on a QEMU/KVM guest running on 2.4GHz Westmere hardware)17:35
somlo_haven't actually tried programming the board (it's at the office), so I'll do that tomorrow17:36
somlo_that's for the rocket-chip based blinky, to be precise17:37
somlo_oh, and that was before you force-pushed a newer version of the PR17:39
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sxpertok, I did what I wanted with another solution ;-)17:43
sxpert(do some of the stuff in a previous phase...17:43
sxpertas in, an actual different clock phase17:44
sxpert(add moar registers)17:44
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sxpertlooks like the instruction set I'm going for is too complicated, needs more thought, single cycle instructions are not really doable17:48
sxpertthe original is probably microprogrammed17:49
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corecodesxpert: what are you making?18:21
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sxpertcorecode: implementing a saturn architecture21:11
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