Saturday, 2019-02-09

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tpbTitle: hp-saturn/hp48_02_sys_ram.v at master · sxpert/hp-saturn · GitHub (at
sxpertseems to be fixed00:03
sxpertah, there's still something wrong though00:04
sxpertnow, to debug what next_pnr states is "ERROR: timing analysis failed due to presence of combinatorial loops, incomplete specification of timing ports, etc."00:25
daveshahsxpert: what happens if you grep the Yosys output for DLATCH?00:29
tpbTitle: Untitled - Pastebin (at
sxpertah, it complains about bus nibble_out[3:0]00:57
sxpertguess I see why...00:58
sxpertwill have to do that some other way...00:58
sxpertalways @(*)00:58
sxpertappears evil00:59
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promach_finnb ZipCPU: I have summarized the verilog code issues at
tpbTitle: Problem with seeing internal generate variable and coverage failed issue with signed multiplication verilog code - Stack Overflow (at
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ZipCPUpromach_: The tools are open source.  The standard is on line.  The VCD format is public/published.  Why not dig into the problem and figure out what's going on for yourself?03:10
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sxpertdaveshah: there, all fixed (after a good night sleep)08:48
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promach_ZipCPU : I have made cover(in_valid) passed09:21
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ZipCPUpromach_: What was the issue?12:36
promach_I did a couple of changes12:37
promach_not sure which one got it work12:37
ZipCPUGo on12:37
promach_ZipCPU: see the diff for the current revision of multiply.v
tpbTitle: A signed multiply verilog code using row adder tree multiplier and modified baugh-wooley algorithm · GitHub (at
promach_ZipCPU: shall we discuss later ? you can leave message here. I will be able to see them later12:38
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ZipCPULooks like voodoo changes to me.  "Voodoo computing, n: to change what isn't broken in an effort to fix what is"12:40
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